Commit b0f89cf5 authored by Michal Simek's avatar Michal Simek
Browse files

arm64: dts: zynqmp: Add DisplayPort subsystem 



Add a DT node for the DisplayPort subsystem, a hard IP present in the
Zynq Ultrascale+ MPSoC.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/4d978aef852cacdfb35aa8e50d648a787e73b90c.1611232558.git.michal.simek@xilinx.com
parent 7b6714b3

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -231,3 +231,9 @@ &lpd_watchdog { 
&zynqmp_dpdma {

	clocks = <&zynqmp_clk DPDMA_REF>;

};



&zynqmp_dpsub {

	clocks = <&zynqmp_clk TOPSW_LSBUS>,

		 <&zynqmp_clk DP_AUDIO_REF>,

		 <&zynqmp_clk DP_VIDEO_REF>;

};

arch/arm64/boot/dts/xilinx/zynqmp.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
 * the License, or (at your option) any later version.

 */



#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>

#include <dt-bindings/power/xlnx-zynqmp-power.h>

#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
@@ -857,5 +858,26 @@ zynqmp_dpdma: dma-controller@fd4c0000 { 
			clock-names = "axi_clk";

			#dma-cells = <1>;

		};



		zynqmp_dpsub: display@fd4a0000 {

			compatible = "xlnx,zynqmp-dpsub-1.7";

			status = "disabled";

			reg = <0x0 0xfd4a0000 0x0 0x1000>,

			      <0x0 0xfd4aa000 0x0 0x1000>,

			      <0x0 0xfd4ab000 0x0 0x1000>,

			      <0x0 0xfd4ac000 0x0 0x1000>;

			reg-names = "dp", "blend", "av_buf", "aud";

			interrupts = <0 119 4>;

			interrupt-parent = <&gic>;

			clock-names = "dp_apb_clk", "dp_aud_clk",

				      "dp_vtc_pixel_clk_in";

			power-domains = <&zynqmp_firmware PD_DP>;

			resets = <&zynqmp_reset ZYNQMP_RESET_DP>;

			dma-names = "vid0", "vid1", "vid2", "gfx0";

			dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,

			       <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,

			       <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,

			       <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;

		};

	};

};