Commit b4c55e52 authored by Eric Yang's avatar Eric Yang Committed by Alex Deucher
Browse files

drm/amd/display: support new PMFW interface to disable Z9 only 



[Why]
Need to disable Z9 on configurations that only support Z10

[How]
Support new PMFW interface to disable Z9

Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarEric Yang <Eric.Yang2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fd9048dd

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c

+3 −3
Original line number Diff line number Diff line
@@ -139,9 +139,9 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, 
	 * also if safe to lower is false, we just go in the higher state

	 */

	if (safe_to_lower) {

		if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_ALLOW &&

		if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&

				new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {

			dcn31_smu_set_Z9_support(clk_mgr, true);

			dcn31_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);

			dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);

			clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;

		}
@@ -167,7 +167,7 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, 
	} else {

		if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&

				new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {

			dcn31_smu_set_Z9_support(clk_mgr, false);

			dcn31_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);

			dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);

			clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;

		}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.c

+10 −5
Original line number Diff line number Diff line
@@ -306,23 +306,28 @@ void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) 
			VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);

}



void dcn31_smu_set_Z9_support(struct clk_mgr_internal *clk_mgr, bool support)

void dcn31_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support)

{

	//TODO: Work with smu team to define optimization options.

	unsigned int msg_id;

	unsigned int msg_id, param;



	if (!clk_mgr->smu_present)

		return;



	if (support)

		msg_id = VBIOSSMC_MSG_AllowZstatesEntry;

	if (support == DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY)

		param = 1;

	else

		param = 0;



	if (support == DCN_ZSTATE_SUPPORT_DISALLOW)

		msg_id = VBIOSSMC_MSG_DisallowZstatesEntry;

	else

		msg_id = VBIOSSMC_MSG_AllowZstatesEntry;



	dcn31_smu_send_msg_with_param(

		clk_mgr,

		msg_id,

		0);

		param);



}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_smu.h

+1 −1
Original line number Diff line number Diff line
@@ -265,7 +265,7 @@ void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr 
void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);

void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);



void dcn31_smu_set_Z9_support(struct clk_mgr_internal *clk_mgr, bool support);

void dcn31_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support);

void dcn31_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);



#endif /* DAL_DC_31_SMU_H_ */

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -396,6 +396,7 @@ enum dcn_pwr_state { 
enum dcn_zstate_support_state {

	DCN_ZSTATE_SUPPORT_UNKNOWN,

	DCN_ZSTATE_SUPPORT_ALLOW,

	DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,

	DCN_ZSTATE_SUPPORT_DISALLOW,

};

#endif

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+7 −1
Original line number Diff line number Diff line
@@ -3093,8 +3093,14 @@ static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struc 
	else if (context->stream_count == 1 &&  context->streams[0]->signal == SIGNAL_TYPE_EDP) {

		struct dc_link *link = context->streams[0]->sink->link;



		if (link->link_index == 0 && context->bw_ctx.dml.vba.StutterPeriod > 5000.0)

		/* zstate only supported on PWRSEQ0 */

		if (link->link_index != 0)

			return DCN_ZSTATE_SUPPORT_DISALLOW;



		if (context->bw_ctx.dml.vba.StutterPeriod > 5000.0)

			return DCN_ZSTATE_SUPPORT_ALLOW;

		else if (link->psr_settings.psr_feature_enabled)

			return DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY;

		else

			return DCN_ZSTATE_SUPPORT_DISALLOW;

	} else