Commit b523d6b8 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/docs' into for-next/core 

* for-next/docs:
  arm64/mte: Clarify mode reported by PR_GET_TAGGED_ADDR_CTRL
  arm64: booting.rst: Clarify on requiring non-secure EL2
parents 0d3d0315 4c022f57

Documentation/arm64/booting.rst

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@@ -10,9 +10,9 @@ This document is based on the ARM booting document by Russell King and 
is relevant to all public releases of the AArch64 Linux kernel.

is relevant to all public releases of the AArch64 Linux kernel.





The AArch64 exception model is made up of a number of exception levels

The AArch64 exception model is made up of a number of exception levels

(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure

(EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure

counterpart.  EL2 is the hypervisor level and exists only in non-secure

counterpart.  EL2 is the hypervisor level, EL3 is the highest priority

mode. EL3 is the highest priority level and exists only in secure mode.

level and exists only in secure mode. Both are architecturally optional.





For the purposes of this document, we will use the term `boot loader`

For the purposes of this document, we will use the term `boot loader`

simply to define all software that executes on the CPU(s) before control

simply to define all software that executes on the CPU(s) before control
@@ -167,8 +167,8 @@ Before jumping into the kernel, the following conditions must be met: 




  All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,

  All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,

  IRQ and FIQ).

  IRQ and FIQ).

  The CPU must be in either EL2 (RECOMMENDED in order to have access to

  The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order

  the virtualisation extensions) or non-secure EL1.

  to have access to the virtualisation extensions), or in EL1.





- Caches, MMUs

- Caches, MMUs

Documentation/arm64/memory-tagging-extension.rst

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@@ -91,8 +91,9 @@ mode is specified, the program will run in that mode. If multiple 
modes are specified, the mode is selected as described in the "Per-CPU

modes are specified, the mode is selected as described in the "Per-CPU

preferred tag checking modes" section below.

preferred tag checking modes" section below.





The current tag check fault mode can be read using the

The current tag check fault configuration can be read using the

``prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0)`` system call.

``prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0)`` system call. If

multiple modes were requested then all will be reported.





Tag checking can also be disabled for a user thread by setting the

Tag checking can also be disabled for a user thread by setting the

``PSTATE.TCO`` bit with ``MSR TCO, #1``.

``PSTATE.TCO`` bit with ``MSR TCO, #1``.