Unverified Commit b558c6fd authored by Richard Fitzgerald's avatar Richard Fitzgerald Committed by Mark Brown
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ASoC: cs42l42: Add SOFT_RESET_REBOOT register 



The SOFT_RESET_REBOOT register is needed to recover CS42L42 state after
a Soundwire bus reset.

This is required to be set whenever there is severe/hard bus reset.

Signed-off-by: default avatarRichard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: default avatarStefan Binding <sbinding@opensource.cirrus.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20230127165111.3010960-3-sbinding@opensource.cirrus.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 43f1a7f9

include/sound/cs42l42.h

+5 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 
#define CS42L42_PAGE_24		0x2400

#define CS42L42_PAGE_25		0x2500

#define CS42L42_PAGE_26		0x2600

#define CS42L42_PAGE_27		0x2700

#define CS42L42_PAGE_28		0x2800

#define CS42L42_PAGE_29		0x2900

#define CS42L42_PAGE_2A		0x2A00
@@ -720,6 +721,10 @@ 


#define CS42L42_SRC_SDOUT_FS		(CS42L42_PAGE_26 + 0x09)



/* Page 0x27 DMA */

#define CS42L42_SOFT_RESET_REBOOT	(CS42L42_PAGE_27 + 0x01)

#define CS42L42_SFT_RST_REBOOT_MASK	BIT(1)



/* Page 0x28 S/PDIF Registers */

#define CS42L42_SPDIF_CTL1		(CS42L42_PAGE_28 + 0x01)

#define CS42L42_SPDIF_CTL2		(CS42L42_PAGE_28 + 0x02)

sound/soc/codecs/cs42l42.c

+2 −0
Original line number Diff line number Diff line
@@ -293,6 +293,7 @@ bool cs42l42_readable_register(struct device *dev, unsigned int reg) 
	case CS42L42_SPDIF_SW_CTL1:

	case CS42L42_SRC_SDIN_FS:

	case CS42L42_SRC_SDOUT_FS:

	case CS42L42_SOFT_RESET_REBOOT:

	case CS42L42_SPDIF_CTL1:

	case CS42L42_SPDIF_CTL2:

	case CS42L42_SPDIF_CTL3:
@@ -358,6 +359,7 @@ bool cs42l42_volatile_register(struct device *dev, unsigned int reg) 
	case CS42L42_LOAD_DET_DONE:

	case CS42L42_DET_STATUS1:

	case CS42L42_DET_STATUS2:

	case CS42L42_SOFT_RESET_REBOOT:

		return true;

	default:

		return false;