Commit b5bc16ab authored by James Clark's avatar James Clark Committed by Mathieu Poirier
Browse files

coresight: etm4x: Cleanup TRCSTALLCTLR register accesses 



This is a no-op change for style and consistency and has no effect on
the binary output by the compiler. In sysreg.h fields are defined as
the register name followed by the field name and then _MASK. This
allows for grepping for fields by name rather than using magic numbers.

Signed-off-by: default avatarJames Clark <james.clark@arm.com>
Reviewed-by: default avatarMike Leach <mike.leach@linaro.org>
Link: https://lore.kernel.org/r/20220304171913.2292458-9-james.clark@arm.com


Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
parent eeae6ddd

drivers/hwtracing/coresight/coresight-etm4x-sysfs.c

+6 −6
Original line number Diff line number Diff line
@@ -397,22 +397,22 @@ static ssize_t mode_store(struct device *dev, 


	/* bit[8], Instruction stall bit */

	if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true))

		config->stall_ctrl |= BIT(8);

		config->stall_ctrl |= TRCSTALLCTLR_ISTALL;

	else

		config->stall_ctrl &= ~BIT(8);

		config->stall_ctrl &= ~TRCSTALLCTLR_ISTALL;



	/* bit[10], Prioritize instruction trace bit */

	if (config->mode & ETM_MODE_INSTPRIO)

		config->stall_ctrl |= BIT(10);

		config->stall_ctrl |= TRCSTALLCTLR_INSTPRIORITY;

	else

		config->stall_ctrl &= ~BIT(10);

		config->stall_ctrl &= ~TRCSTALLCTLR_INSTPRIORITY;



	/* bit[13], Trace overflow prevention bit */

	if ((config->mode & ETM_MODE_NOOVERFLOW) &&

		(drvdata->nooverflow == true))

		config->stall_ctrl |= BIT(13);

		config->stall_ctrl |= TRCSTALLCTLR_NOOVERFLOW;

	else

		config->stall_ctrl &= ~BIT(13);

		config->stall_ctrl &= ~TRCSTALLCTLR_NOOVERFLOW;



	/* bit[9] Start/stop logic control bit */

	if (config->mode & ETM_MODE_VIEWINST_STARTSTOP)

drivers/hwtracing/coresight/coresight-etm4x.h

+4 −0
Original line number Diff line number Diff line
@@ -196,6 +196,10 @@ 
#define TRCEVENTCTL1R_ATB			BIT(11)

#define TRCEVENTCTL1R_LPOVERRIDE		BIT(12)



#define TRCSTALLCTLR_ISTALL			BIT(8)

#define TRCSTALLCTLR_INSTPRIORITY		BIT(10)

#define TRCSTALLCTLR_NOOVERFLOW			BIT(13)



/*

 * System instructions to access ETM registers.

 * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions