Commit b6007ff8 authored by Jiaxun Yang's avatar Jiaxun Yang Committed by Thomas Bogendoerfer
Browse files

MIPS: Octeon: Allow CVMSEG to be disabled 



Don't include cvmseg states into thread_status when
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE is not defined or 0.

Fix compile for kernel without this feature.

Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 6e900491

arch/mips/include/asm/processor.h

+6 −1
Original line number Diff line number Diff line
@@ -202,11 +202,13 @@ struct octeon_cop2_state { 
#define COP2_INIT						\

	.cp2			= {0,},



#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \

	CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0

struct octeon_cvmseg_state {

	unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]

			    [cpu_dcache_line_size() / sizeof(unsigned long)];

};



#endif

#else

#define COP2_INIT

#endif
@@ -263,7 +265,10 @@ struct thread_struct { 
	unsigned long trap_nr;

#ifdef CONFIG_CPU_CAVIUM_OCTEON

	struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));

#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \

	CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0

	struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));

#endif

#endif

	struct mips_abi *abi;

};

arch/mips/kernel/asm-offsets.c

+3 −0
Original line number Diff line number Diff line
@@ -306,7 +306,10 @@ void output_octeon_cop2_state_defines(void) 
	OFFSET(OCTEON_CP2_HSH_IVW,	octeon_cop2_state, cop2_hsh_ivw);

	OFFSET(OCTEON_CP2_SHA3,		octeon_cop2_state, cop2_sha3);

	OFFSET(THREAD_CP2,	task_struct, thread.cp2);

#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \

    CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0

	OFFSET(THREAD_CVMSEG,	task_struct, thread.cvmseg.cvmseg);

#endif

	BLANK();

}

#endif