Loading arch/sh/include/asm/clock.h +2 −1 Original line number Diff line number Diff line Loading @@ -12,7 +12,7 @@ struct clk_ops { void (*init)(struct clk *clk); void (*enable)(struct clk *clk); void (*disable)(struct clk *clk); void (*recalc)(struct clk *clk); unsigned long (*recalc)(struct clk *clk); int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); int (*set_parent)(struct clk *clk, struct clk *parent); long (*round_rate)(struct clk *clk, unsigned long rate); Loading Loading @@ -96,4 +96,5 @@ enum clk_sh_algo_id { IP_N1, }; #endif /* __ASM_SH_CLOCK_H */ arch/sh/kernel/cpu/clock.c +19 −16 Original line number Diff line number Diff line Loading @@ -75,6 +75,7 @@ static struct clk *onchip_clocks[] = { &cpu_clk, }; /* Propagate rate to children */ static void propagate_rate(struct clk *clk) { struct clk *clkp; Loading @@ -83,7 +84,7 @@ static void propagate_rate(struct clk *clk) if (likely(clkp->parent != clk)) continue; if (likely(clkp->ops && clkp->ops->recalc)) clkp->ops->recalc(clkp); clkp->rate = clkp->ops->recalc(clkp); if (unlikely(clkp->flags & CLK_RATE_PROPAGATES)) propagate_rate(clkp); } Loading Loading @@ -240,7 +241,7 @@ void clk_recalc_rate(struct clk *clk) unsigned long flags; spin_lock_irqsave(&clock_lock, flags); clk->ops->recalc(clk); clk->rate = clk->ops->recalc(clk); spin_unlock_irqrestore(&clock_lock, flags); } Loading Loading @@ -377,8 +378,10 @@ static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state) switch (state.event) { case PM_EVENT_ON: /* Resumeing from hibernation */ if (prev_state.event == PM_EVENT_FREEZE) { list_for_each_entry(clkp, &clock_list, node) if (prev_state.event != PM_EVENT_FREEZE) break; list_for_each_entry(clkp, &clock_list, node) { if (likely(clkp->ops)) { unsigned long rate = clkp->rate; Loading @@ -389,7 +392,7 @@ static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state) clkp->ops->set_rate(clkp, rate, NO_CHANGE); else if (likely(clkp->ops->recalc)) clkp->ops->recalc(clkp); clkp->rate = clkp->ops->recalc(clkp); } } break; Loading arch/sh/kernel/cpu/sh2/clock-sh7619.c +6 −7 Original line number Diff line number Diff line Loading @@ -38,28 +38,28 @@ static struct clk_ops sh7619_master_clk_ops = { .init = master_clk_init, }; static void module_clk_recalc(struct clk *clk) static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); clk->rate = clk->parent->rate / pfc_divisors[idx]; return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7619_module_clk_ops = { .recalc = module_clk_recalc, }; static void bus_clk_recalc(struct clk *clk) static unsigned long bus_clk_recalc(struct clk *clk) { clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7]; return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7]; } static struct clk_ops sh7619_bus_clk_ops = { .recalc = bus_clk_recalc, }; static void cpu_clk_recalc(struct clk *clk) static unsigned long cpu_clk_recalc(struct clk *clk) { clk->rate = clk->parent->rate; return clk->parent->rate; } static struct clk_ops sh7619_cpu_clk_ops = { Loading @@ -78,4 +78,3 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx) if (idx < ARRAY_SIZE(sh7619_clk_ops)) *ops = sh7619_clk_ops[idx]; } arch/sh/kernel/cpu/sh2a/clock-sh7201.c +7 −7 Original line number Diff line number Diff line Loading @@ -34,37 +34,37 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12}; static void master_clk_init(struct clk *clk) { clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; return 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; } static struct clk_ops sh7201_master_clk_ops = { .init = master_clk_init, }; static void module_clk_recalc(struct clk *clk) static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); clk->rate = clk->parent->rate / pfc_divisors[idx]; return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7201_module_clk_ops = { .recalc = module_clk_recalc, }; static void bus_clk_recalc(struct clk *clk) static unsigned long bus_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); clk->rate = clk->parent->rate / pfc_divisors[idx]; return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7201_bus_clk_ops = { .recalc = bus_clk_recalc, }; static void cpu_clk_recalc(struct clk *clk) static unsigned long cpu_clk_recalc(struct clk *clk) { int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007); clk->rate = clk->parent->rate / ifc_divisors[idx]; return clk->parent->rate / ifc_divisors[idx]; } static struct clk_ops sh7201_cpu_clk_ops = { Loading arch/sh/kernel/cpu/sh2a/clock-sh7203.c +6 −6 Original line number Diff line number Diff line Loading @@ -46,29 +46,29 @@ static struct clk_ops sh7203_master_clk_ops = { .init = master_clk_init, }; static void module_clk_recalc(struct clk *clk) static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); clk->rate = clk->parent->rate / pfc_divisors[idx]; return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7203_module_clk_ops = { .recalc = module_clk_recalc, }; static void bus_clk_recalc(struct clk *clk) static unsigned long bus_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); clk->rate = clk->parent->rate / pfc_divisors[idx-2]; return clk->parent->rate / pfc_divisors[idx-2]; } static struct clk_ops sh7203_bus_clk_ops = { .recalc = bus_clk_recalc, }; static void cpu_clk_recalc(struct clk *clk) static unsigned long cpu_clk_recalc(struct clk *clk) { clk->rate = clk->parent->rate; return clk->parent->rate; } static struct clk_ops sh7203_cpu_clk_ops = { Loading Loading
arch/sh/include/asm/clock.h +2 −1 Original line number Diff line number Diff line Loading @@ -12,7 +12,7 @@ struct clk_ops { void (*init)(struct clk *clk); void (*enable)(struct clk *clk); void (*disable)(struct clk *clk); void (*recalc)(struct clk *clk); unsigned long (*recalc)(struct clk *clk); int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); int (*set_parent)(struct clk *clk, struct clk *parent); long (*round_rate)(struct clk *clk, unsigned long rate); Loading Loading @@ -96,4 +96,5 @@ enum clk_sh_algo_id { IP_N1, }; #endif /* __ASM_SH_CLOCK_H */
arch/sh/kernel/cpu/clock.c +19 −16 Original line number Diff line number Diff line Loading @@ -75,6 +75,7 @@ static struct clk *onchip_clocks[] = { &cpu_clk, }; /* Propagate rate to children */ static void propagate_rate(struct clk *clk) { struct clk *clkp; Loading @@ -83,7 +84,7 @@ static void propagate_rate(struct clk *clk) if (likely(clkp->parent != clk)) continue; if (likely(clkp->ops && clkp->ops->recalc)) clkp->ops->recalc(clkp); clkp->rate = clkp->ops->recalc(clkp); if (unlikely(clkp->flags & CLK_RATE_PROPAGATES)) propagate_rate(clkp); } Loading Loading @@ -240,7 +241,7 @@ void clk_recalc_rate(struct clk *clk) unsigned long flags; spin_lock_irqsave(&clock_lock, flags); clk->ops->recalc(clk); clk->rate = clk->ops->recalc(clk); spin_unlock_irqrestore(&clock_lock, flags); } Loading Loading @@ -377,8 +378,10 @@ static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state) switch (state.event) { case PM_EVENT_ON: /* Resumeing from hibernation */ if (prev_state.event == PM_EVENT_FREEZE) { list_for_each_entry(clkp, &clock_list, node) if (prev_state.event != PM_EVENT_FREEZE) break; list_for_each_entry(clkp, &clock_list, node) { if (likely(clkp->ops)) { unsigned long rate = clkp->rate; Loading @@ -389,7 +392,7 @@ static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state) clkp->ops->set_rate(clkp, rate, NO_CHANGE); else if (likely(clkp->ops->recalc)) clkp->ops->recalc(clkp); clkp->rate = clkp->ops->recalc(clkp); } } break; Loading
arch/sh/kernel/cpu/sh2/clock-sh7619.c +6 −7 Original line number Diff line number Diff line Loading @@ -38,28 +38,28 @@ static struct clk_ops sh7619_master_clk_ops = { .init = master_clk_init, }; static void module_clk_recalc(struct clk *clk) static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); clk->rate = clk->parent->rate / pfc_divisors[idx]; return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7619_module_clk_ops = { .recalc = module_clk_recalc, }; static void bus_clk_recalc(struct clk *clk) static unsigned long bus_clk_recalc(struct clk *clk) { clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7]; return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7]; } static struct clk_ops sh7619_bus_clk_ops = { .recalc = bus_clk_recalc, }; static void cpu_clk_recalc(struct clk *clk) static unsigned long cpu_clk_recalc(struct clk *clk) { clk->rate = clk->parent->rate; return clk->parent->rate; } static struct clk_ops sh7619_cpu_clk_ops = { Loading @@ -78,4 +78,3 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx) if (idx < ARRAY_SIZE(sh7619_clk_ops)) *ops = sh7619_clk_ops[idx]; }
arch/sh/kernel/cpu/sh2a/clock-sh7201.c +7 −7 Original line number Diff line number Diff line Loading @@ -34,37 +34,37 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12}; static void master_clk_init(struct clk *clk) { clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; return 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; } static struct clk_ops sh7201_master_clk_ops = { .init = master_clk_init, }; static void module_clk_recalc(struct clk *clk) static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); clk->rate = clk->parent->rate / pfc_divisors[idx]; return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7201_module_clk_ops = { .recalc = module_clk_recalc, }; static void bus_clk_recalc(struct clk *clk) static unsigned long bus_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); clk->rate = clk->parent->rate / pfc_divisors[idx]; return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7201_bus_clk_ops = { .recalc = bus_clk_recalc, }; static void cpu_clk_recalc(struct clk *clk) static unsigned long cpu_clk_recalc(struct clk *clk) { int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007); clk->rate = clk->parent->rate / ifc_divisors[idx]; return clk->parent->rate / ifc_divisors[idx]; } static struct clk_ops sh7201_cpu_clk_ops = { Loading
arch/sh/kernel/cpu/sh2a/clock-sh7203.c +6 −6 Original line number Diff line number Diff line Loading @@ -46,29 +46,29 @@ static struct clk_ops sh7203_master_clk_ops = { .init = master_clk_init, }; static void module_clk_recalc(struct clk *clk) static unsigned long module_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); clk->rate = clk->parent->rate / pfc_divisors[idx]; return clk->parent->rate / pfc_divisors[idx]; } static struct clk_ops sh7203_module_clk_ops = { .recalc = module_clk_recalc, }; static void bus_clk_recalc(struct clk *clk) static unsigned long bus_clk_recalc(struct clk *clk) { int idx = (ctrl_inw(FREQCR) & 0x0007); clk->rate = clk->parent->rate / pfc_divisors[idx-2]; return clk->parent->rate / pfc_divisors[idx-2]; } static struct clk_ops sh7203_bus_clk_ops = { .recalc = bus_clk_recalc, }; static void cpu_clk_recalc(struct clk *clk) static unsigned long cpu_clk_recalc(struct clk *clk) { clk->rate = clk->parent->rate; return clk->parent->rate; } static struct clk_ops sh7203_cpu_clk_ops = { Loading