dt-bindings: PCI: convert amlogic,meson-pcie.txt to dt-schema

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Amlogic Meson AXG DWC PCIe SoC controller

maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>

description:

  Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.

allOf:

  - $ref: /schemas/pci/pci-bus.yaml#

  - $ref: /schemas/pci/snps,dw-pcie-common.yaml#

# We need a select here so we don't match all nodes with 'snps,dw-pcie'

select:

  properties:

    compatible:

      enum:

        - amlogic,axg-pcie

        - amlogic,g12a-pcie

  required:

    - compatible

properties:

  compatible:

    items:

      - enum:

          - amlogic,axg-pcie

          - amlogic,g12a-pcie

      - const: snps,dw-pcie

  reg:

    items:

      - description: External local bus interface registers

      - description: Meson designed configuration registers

      - description: PCIe configuration space

  reg-names:

    items:

      - const: elbi

      - const: cfg

      - const: config

  interrupts:

    maxItems: 1

  clocks:

    items:

      - description: PCIe GEN 100M PLL clock

      - description: PCIe RC clock gate

      - description: PCIe PHY clock

  clock-names:

    items:

      - const: pclk

      - const: port

      - const: general

  phys:

    maxItems: 1

  phy-names:

    const: pcie

  resets:

    items:

      - description: Port Reset

      - description: Shared APB reset

  reset-names:

    items:

      - const: port

      - const: apb

  num-lanes:

    const: 1

  power-domains:

    maxItems: 1

required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - clock

  - clock-names

  - "#address-cells"

  - "#size-cells"

  - "#interrupt-cells"

  - interrupt-map

  - interrupt-map-mask

  - ranges

  - bus-range

  - device_type

  - num-lanes

  - phys

  - phy-names

  - resets

  - reset-names

unevaluatedProperties: false

examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    pcie: pcie@f9800000 {

        compatible = "amlogic,axg-pcie", "snps,dw-pcie";

        reg = <0xf9800000 0x400000>, <0xff646000 0x2000>, <0xf9f00000 0x100000>;

        reg-names = "elbi", "cfg", "config";

        interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;

        clocks = <&pclk>, <&clk_port>, <&clk_phy>;

        clock-names = "pclk", "port", "general";

        resets = <&reset_pcie_port>, <&reset_pcie_apb>;

        reset-names = "port", "apb";

        phys = <&pcie_phy>;

        phy-names = "pcie";

        #interrupt-cells = <1>;

        interrupt-map-mask = <0 0 0 0>;

        interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;

        bus-range = <0x0 0xff>;

        #address-cells = <3>;

        #size-cells = <2>;

        device_type = "pci";

        num-lanes = <1>;

        ranges = <0x82000000 0 0 0xf9c00000 0 0x00300000>;

    };

...

Amlogic Meson AXG DWC PCIE SoC controller

Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.

It shares common functions with the PCIe DesignWare core driver and

inherits common properties defined in

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.

Additional properties are described here:

Required properties:

- compatible:

	should contain :

	- "amlogic,axg-pcie" for AXG SoC Family

	- "amlogic,g12a-pcie" for G12A SoC Family

	to identify the core.

- reg:

	should contain the configuration address space.

- reg-names: Must be

	- "elbi"	External local bus interface registers

	- "cfg"		Meson specific registers

	- "config"	PCIe configuration space

- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.

- clocks: Must contain an entry for each entry in clock-names.

- clock-names: Must include the following entries:

	- "pclk"       PCIe GEN 100M PLL clock

	- "port"       PCIe_x(A or B) RC clock gate

	- "general"    PCIe Phy clock

- resets: phandle to the reset lines.

- reset-names: must contain "port" and "apb"

       - "port"        Port A or B reset

       - "apb"         Share APB reset

- phys: should contain a phandle to the PCIE phy

- phy-names: must contain "pcie"

- device_type:

	should be "pci". As specified in snps,dw-pcie.yaml

Example configuration:

	pcie: pcie@f9800000 {

			compatible = "amlogic,axg-pcie", "snps,dw-pcie";

			reg = <0x0 0xf9800000 0x0 0x400000

					0x0 0xff646000 0x0 0x2000

					0x0 0xf9f00000 0x0 0x100000>;

			reg-names = "elbi", "cfg", "config";

			reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;

			interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;

			bus-range = <0x0 0xff>;

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;

			clocks = <&clkc CLKID_USB

					&clkc CLKID_PCIE_A

					&clkc CLKID_PCIE_CML_EN0>;

			clock-names = "general",

					"pclk",

					"port";

			resets = <&reset RESET_PCIE_A>,

				<&reset RESET_PCIE_APB>;

			reset-names = "port",

					"apb";

			phys = <&pcie_phy>;

			phy-names = "pcie";

	};