Commit b8e3a0ff authored by Chris Morgan's avatar Chris Morgan Committed by Heiko Stuebner
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arm64: dts: rockchip: don't set cpll rate for Odroid Go 



The Odroid Go Advance devicetree tries to set the rate for the cpll
clock to 17MHz, which is not a supported rate. This fails, and triggers
the error of "clk: couldn't set cpll clk rate to 17000000 (-22),
current rate: 17000000" in the dmesg log. Remove the incorrect rate.

Signed-off-by: default avatarChris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20221201203655.1245-3-macroalpha82@gmail.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 0d434398

arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi

+2 −4
Original line number Diff line number Diff line
@@ -192,14 +192,12 @@ &cru { 
	assigned-clocks = <&cru PLL_NPLL>,

		<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,

		<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,

		<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,

		<&cru PLL_CPLL>;

		<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;



	assigned-clock-rates = <1188000000>,

		<200000000>, <200000000>,

		<150000000>, <150000000>,

		<100000000>, <200000000>,

		<17000000>;

		<100000000>, <200000000>;

};



&display_subsystem {