Commit b97b1a76 authored by Michael Walle's avatar Michael Walle Committed by Vignesh Raghavendra
Browse files

mtd: spi-nor: otp: fix access to security registers in 4 byte mode 



The security registers either take a 3 byte or a 4 byte address offset,
depending on the address mode of the flash. Thus just leave the
nor->addr_width as is.

Fixes: cad3193f ("mtd: spi-nor: implement OTP support for Winbond and similar flashes")
Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
Acked-by: default avatarPratyush Yadav <p.yadav@ti.com>
parent 7ea40b54

drivers/mtd/spi-nor/otp.c

+0 −2
Original line number Diff line number Diff line
@@ -40,7 +40,6 @@ int spi_nor_otp_read_secr(struct spi_nor *nor, loff_t addr, size_t len, u8 *buf) 
	rdesc = nor->dirmap.rdesc;



	nor->read_opcode = SPINOR_OP_RSECR;

	nor->addr_width = 3;

	nor->read_dummy = 8;

	nor->read_proto = SNOR_PROTO_1_1_1;

	nor->dirmap.rdesc = NULL;
@@ -84,7 +83,6 @@ int spi_nor_otp_write_secr(struct spi_nor *nor, loff_t addr, size_t len, 
	wdesc = nor->dirmap.wdesc;



	nor->program_opcode = SPINOR_OP_PSECR;

	nor->addr_width = 3;

	nor->write_proto = SNOR_PROTO_1_1_1;

	nor->dirmap.wdesc = NULL;