Unverified Commit ba232d39 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v5.15-next-dts64' of... 

Merge tag 'v5.15-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

Biggest change is, that we have now support for a reset controller inside the
mmsys. This goes inhand with changes to the driver, that you will find in the
soc pull request.

Mediatek PCI device tree binding described the root port in a wrong. The IP
actaully implements several root complex with everyone having a single root port.

We need to fix the DT in an incompatible way to describe the HW as it is. This
also fixes a problem that no IRQ bigger then 32 could be handled.

The only public available HW that is affected by this is the BananaPi R64. I'm
not aware that there is a big user base using the upstream kernel. In this
boards PCI is only used for extension cards, so I don't expect any boot problems.

- mt8173: add reset for dsi0 to mmsys
- move dt-bindings reset controller includes to correct folder
- split PCIe node to use new format for mt2712 and mt7622
- mt8183: add audio node to chromebook devices
- mt8192: add clock controller node

* tag 'v5.15-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: mt8183: Add the mmsys reset bit to reset the dsi0
  arm64: dts: mt8173: Add the mmsys reset bit to reset the dsi0
  dt-bindings: display: mediatek: add dsi reset optional property
  dt-bindings: mediatek: Add #reset-cells to mmsys system controller
  arm64: dts: mediatek: Move reset controller constants into common location
  arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622
  arm64: dts: mt8183: add kukui platform audio node
  arm64: dts: mt8183: add audio node
  arm64: dts: mediatek: Add mt8192 clock controllers

Link: https://lore.kernel.org/r/1a3d63a3-c020-3319-26f6-a2ec338cc42e@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 96c7f32d 4bdb00ed

Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml

+4 −0
Original line number Diff line number Diff line
@@ -43,6 +43,9 @@ properties: 
  "#clock-cells":

    const: 1



  '#reset-cells':

    const: 1



required:

  - compatible

  - reg
@@ -56,4 +59,5 @@ examples: 
        compatible = "mediatek,mt8173-mmsys", "syscon";

        reg = <0x14000000 0x1000>;

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt

+6 −0
Original line number Diff line number Diff line
@@ -19,6 +19,11 @@ Required properties: 
  Documentation/devicetree/bindings/graph.txt. This port should be connected

  to the input port of an attached DSI panel or DSI-to-eDP encoder chip.



Optional properties:

- resets: list of phandle + reset specifier pair, as described in [1].



[1] Documentation/devicetree/bindings/reset/reset.txt



MIPI TX Configuration Module

============================
@@ -45,6 +50,7 @@ dsi0: dsi@1401b000 { 
	clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,

		 <&mipi_tx0>;

	clock-names = "engine", "digital", "hs";

	resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;

	phys = <&mipi_tx0>;

	phy-names = "dphy";

arch/arm64/boot/dts/mediatek/mt2712e.dtsi

+50 −47
Original line number Diff line number Diff line
@@ -915,66 +915,69 @@ u3port1: usb-phy@8700 { 
		};

	};



	pcie: pcie@11700000 {

	pcie1: pcie@112ff000 {

		compatible = "mediatek,mt2712-pcie";

		device_type = "pci";

		reg = <0 0x11700000 0 0x1000>,

		      <0 0x112ff000 0 0x1000>;

		reg-names = "port0", "port1";

		reg = <0 0x112ff000 0 0x1000>;

		reg-names = "port1";

		linux,pci-domain = <1>;

		#address-cells = <3>;

		#size-cells = <2>;

		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,

			 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,

			 <&pericfg CLK_PERI_PCIE0>,

		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "pcie_irq";

		clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,

			 <&pericfg CLK_PERI_PCIE1>;

		clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";

		phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;

		phy-names = "pcie-phy0", "pcie-phy1";

		clock-names = "sys_ck1", "ahb_ck1";

		phys = <&u3port1 PHY_TYPE_PCIE>;

		phy-names = "pcie-phy1";

		bus-range = <0x00 0xff>;

		ranges = <0x82000000 0 0x20000000  0x0 0x20000000  0 0x10000000>;



		pcie0: pcie@0,0 {

			device_type = "pci";

		ranges = <0x82000000 0 0x11400000  0x0 0x11400000  0 0x300000>;

		status = "disabled";

			reg = <0x0000 0 0 0 0>;

			#address-cells = <3>;

			#size-cells = <2>;



		#interrupt-cells = <1>;

			ranges;

		interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0 0 0 1 &pcie_intc0 0>,

					<0 0 0 2 &pcie_intc0 1>,

					<0 0 0 3 &pcie_intc0 2>,

					<0 0 0 4 &pcie_intc0 3>;

			pcie_intc0: interrupt-controller {

		interrupt-map = <0 0 0 1 &pcie_intc1 0>,

				<0 0 0 2 &pcie_intc1 1>,

				<0 0 0 3 &pcie_intc1 2>,

				<0 0 0 4 &pcie_intc1 3>;

		pcie_intc1: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		};

	};



		pcie1: pcie@1,0 {

	pcie0: pcie@11700000 {

		compatible = "mediatek,mt2712-pcie";

		device_type = "pci";

			status = "disabled";

			reg = <0x0800 0 0 0 0>;

		reg = <0 0x11700000 0 0x1000>;

		reg-names = "port0";

		linux,pci-domain = <0>;

		#address-cells = <3>;

		#size-cells = <2>;

		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "pcie_irq";

		clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,

			 <&pericfg CLK_PERI_PCIE0>;

		clock-names = "sys_ck0", "ahb_ck0";

		phys = <&u3port0 PHY_TYPE_PCIE>;

		phy-names = "pcie-phy0";

		bus-range = <0x00 0xff>;

		ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;

		status = "disabled";



		#interrupt-cells = <1>;

			ranges;

		interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0 0 0 1 &pcie_intc1 0>,

					<0 0 0 2 &pcie_intc1 1>,

					<0 0 0 3 &pcie_intc1 2>,

					<0 0 0 4 &pcie_intc1 3>;

			pcie_intc1: interrupt-controller {

		interrupt-map = <0 0 0 1 &pcie_intc0 0>,

				<0 0 0 2 &pcie_intc0 1>,

				<0 0 0 3 &pcie_intc0 2>,

				<0 0 0 4 &pcie_intc0 3>;

		pcie_intc0: interrupt-controller {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <1>;

		};

	};

	};



	mfgcfg: syscon@13000000 {

		compatible = "mediatek,mt2712-mfgcfg", "syscon";

arch/arm64/boot/dts/mediatek/mt6358.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ pmic: mt6358 { 


		mt6358codec: mt6358codec {

			compatible = "mediatek,mt6358-sound";

			mediatek,dmic-mode = <0>; /* two-wires */

		};



		mt6358regulator: mt6358regulator {

arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts

+7 −9
Original line number Diff line number Diff line
@@ -257,19 +257,17 @@ flash@0 { 
	};

};



&pcie {

&pcie0 {

	pinctrl-names = "default";

	pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;

	status = "okay";



	pcie@0,0 {

	pinctrl-0 = <&pcie0_pins>;

	status = "okay";

};



	pcie@1,0 {

&pcie1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pcie1_pins>;

	status = "okay";

};

};



&pio {

	/* Attention: GPIO 90 is used to switch between PCIe@1,0 and