Commit ba81bf44 authored by Fabrizio Castro's avatar Fabrizio Castro Committed by Geert Uytterhoeven
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arm64: dts: renesas: r9a09g011: Add CSI nodes 



The Renesas RZ/V2M comes with 6 Clocked Serial Interface (CSI)
IPs (CSI0, CSI1, CSI2, CSI3, CSI4, CSI5), but Linux is only
allowed access to CSI0 and CSI4.

This commit adds SoC specific device tree support for CSI0 and
CSI4.

Signed-off-by: default avatarFabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230622113341.657842-5-fabrizio.castro.jz@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent db673457

arch/arm64/boot/dts/renesas/r9a09g011.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -236,6 +236,34 @@ sys: system-controller@a3f03000 { 
			reg = <0 0xa3f03000 0 0x400>;

		};



		csi0: spi@a4020000 {

			compatible = "renesas,rzv2m-csi";

			reg = <0 0xa4020000 0 0x80>;

			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD R9A09G011_CSI0_CLK>,

				 <&cpg CPG_MOD R9A09G011_CPERI_GRPG_PCLK>;

			clock-names = "csiclk", "pclk";

			resets = <&cpg R9A09G011_CSI_GPG_PRESETN>;

			power-domains = <&cpg>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		csi4: spi@a4020200 {

			compatible = "renesas,rzv2m-csi";

			reg = <0 0xa4020200 0 0x80>;

			interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>,

				 <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;

			clock-names = "csiclk", "pclk";

			resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;

			power-domains = <&cpg>;

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



		i2c0: i2c@a4030000 {

			#address-cells = <1>;

			#size-cells = <0>;