Commit bad720ff authored by Eric Anholt's avatar Eric Anholt
Browse files

drm/i915: Add initial bits for VGA modesetting bringup on Sandybridge. 



Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 1089e300

drivers/gpu/drm/i915/i915_debugfs.c

+1 −1
Original line number Diff line number Diff line
@@ -162,7 +162,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) 
	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;



	if (!IS_IRONLAKE(dev)) {

	if (!HAS_PCH_SPLIT(dev)) {

		seq_printf(m, "Interrupt enable:    %08x\n",

			   I915_READ(IER));

		seq_printf(m, "Interrupt identity:  %08x\n",

drivers/gpu/drm/i915/i915_dma.c

+11 −5
Original line number Diff line number Diff line
@@ -1094,15 +1094,21 @@ static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size, 
	 * Some of the preallocated space is taken by the GTT

	 * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.

	 */

	if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev))

	if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))

		overhead = 4096;

	else

		overhead = (*aperture_size / 1024) + 4096;



	switch (tmp & INTEL_GMCH_GMS_MASK) {

	case INTEL_855_GMCH_GMS_DISABLED:

		/* XXX: This is what my A1 silicon has. */

		if (IS_GEN6(dev)) {

			stolen = 64 * 1024 * 1024;

		} else {

			DRM_ERROR("video memory is disabled\n");

			return -1;

		}

		break;

	case INTEL_855_GMCH_GMS_STOLEN_1M:

		stolen = 1 * 1024 * 1024;

		break;
@@ -1180,7 +1186,7 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev, 
	int gtt_offset, gtt_size;



	if (IS_I965G(dev)) {

		if (IS_G4X(dev) || IS_IRONLAKE(dev)) {

		if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {

			gtt_offset = 2*1024*1024;

			gtt_size = 2*1024*1024;

		} else {
@@ -1563,7 +1569,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 


	dev->driver->get_vblank_counter = i915_get_vblank_counter;

	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */

	if (IS_G4X(dev) || IS_IRONLAKE(dev)) {

	if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {

		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */

		dev->driver->get_vblank_counter = gm45_get_vblank_counter;

	}

drivers/gpu/drm/i915/i915_drv.h

+25 −1
Original line number Diff line number Diff line
@@ -1065,7 +1065,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
#define IS_845G(dev)		((dev)->pci_device == 0x2562)

#define IS_I85X(dev)		((dev)->pci_device == 0x3582)

#define IS_I865G(dev)		((dev)->pci_device == 0x2572)

#define IS_I8XX(dev)		(INTEL_INFO(dev)->is_i8xx)

#define IS_GEN2(dev)		(INTEL_INFO(dev)->is_i8xx)

#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)

#define IS_I915GM(dev)		((dev)->pci_device == 0x2592)

#define IS_I945G(dev)		((dev)->pci_device == 0x2772)
@@ -1084,8 +1084,29 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
#define IS_I9XX(dev)		(INTEL_INFO(dev)->is_i9xx)

#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)



#define IS_GEN3(dev)	(IS_I915G(dev) ||			\

			 IS_I915GM(dev) ||			\

			 IS_I945G(dev) ||			\

			 IS_I945GM(dev) ||			\

			 IS_G33(dev) || \

			 IS_PINEVIEW(dev))

#define IS_GEN4(dev)	((dev)->pci_device == 0x2972 ||		\

			 (dev)->pci_device == 0x2982 ||		\

			 (dev)->pci_device == 0x2992 ||		\

			 (dev)->pci_device == 0x29A2 ||		\

			 (dev)->pci_device == 0x2A02 ||		\

			 (dev)->pci_device == 0x2A12 ||		\

			 (dev)->pci_device == 0x2E02 ||		\

			 (dev)->pci_device == 0x2E12 ||		\

			 (dev)->pci_device == 0x2E22 ||		\

			 (dev)->pci_device == 0x2E32 ||		\

			 (dev)->pci_device == 0x2A42 ||		\

			 (dev)->pci_device == 0x2E42)



#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)



#define IS_GEN6(dev)	((dev)->pci_device == 0x0102)



/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte

 * rows, which changed the alignment requirements and fence programming.

 */
@@ -1106,6 +1127,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); 
#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)

#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)



#define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) ||	\

			    IS_GEN6(dev))



#define PRIMARY_RINGBUFFER_SIZE         (128*1024)



#endif

drivers/gpu/drm/i915/i915_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -1818,7 +1818,7 @@ i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible) 
		return -EIO;



	if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {

		if (IS_IRONLAKE(dev))

		if (HAS_PCH_SPLIT(dev))

			ier = I915_READ(DEIER) | I915_READ(GTIER);

		else

			ier = I915_READ(IER);

drivers/gpu/drm/i915/i915_gem_tiling.c

+1 −1
Original line number Diff line number Diff line
@@ -92,7 +92,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) 
	uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;

	uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;



	if (IS_IRONLAKE(dev)) {

	if (IS_IRONLAKE(dev) || IS_GEN6(dev)) {

		/* On Ironlake whatever DRAM config, GPU always do

		 * same swizzling setup.

		 */