Commit bbfbf09d authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Remove FPU guards from the DML folder 



As part of the programming expectation for using DML functions, DC
requires that any DML function invoked outside DML uses:

 DC_FP_START();
 ... dml function ...
 DC_FP_END();

Additionally, all the DML functions that can be invoked outside the DML
folder call the function dc_assert_fp_enabled(), which is responsible
for triggering a warning in the case that the DML function was not
guarded by the DC_FP_START/END. For this reason, call DC_FP_START/END
inside DML is wrong, and this commit removes all of those references.

Tested-by: default avatarMark Broadworth <mark.broadworth@amd.com>
Reviewed-by: default avatarNevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b66fca42

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

+0 −2
Original line number Original line Diff line number Diff line
@@ -520,9 +520,7 @@ void dcn30_fpu_calculate_wm_and_dlg( 
		pipe_idx++;

		pipe_idx++;

	}

	}





	DC_FP_START();

	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

	DC_FP_END();





	if (!pstate_en)

	if (!pstate_en)

		/* Restore full p-state latency */

		/* Restore full p-state latency */

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+1 −16
Original line number Original line Diff line number Diff line
@@ -1191,9 +1191,7 @@ static void dcn32_full_validate_bw_helper(struct dc *dc, 
			}

			}

		} else {

		} else {

			// Most populate phantom DLG params before programming hardware / timing for phantom pipe

			// Most populate phantom DLG params before programming hardware / timing for phantom pipe

			DC_FP_START();

			dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);

			dcn32_helper_populate_phantom_dlg_params(dc, context, pipes, *pipe_cnt);

			DC_FP_END();





			/* Call validate_apply_pipe_split flags after calling DML getters for

			/* Call validate_apply_pipe_split flags after calling DML getters for

			 * phantom dlg params, or some of the VBA params indicating pipe split

			 * phantom dlg params, or some of the VBA params indicating pipe split
@@ -1494,11 +1492,8 @@ bool dcn32_internal_validate_bw(struct dc *dc, 




	dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);

	dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);





	if (!fast_validate) {

	if (!fast_validate)

		DC_FP_START();

		dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);

		dcn32_full_validate_bw_helper(dc, context, pipes, &vlevel, split, merge, &pipe_cnt);

		DC_FP_END();

	}





	if (fast_validate ||

	if (fast_validate ||

			(dc->debug.dml_disallow_alternate_prefetch_modes &&

			(dc->debug.dml_disallow_alternate_prefetch_modes &&
@@ -2145,9 +2140,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 
		entry.fabricclk_mhz = 0;

		entry.fabricclk_mhz = 0;

		entry.dram_speed_mts = 0;

		entry.dram_speed_mts = 0;





		DC_FP_START();

		insert_entry_into_table_sorted(table, num_entries, &entry);

		insert_entry_into_table_sorted(table, num_entries, &entry);

		DC_FP_END();

	}

	}





	// Insert the max DCFCLK

	// Insert the max DCFCLK
@@ -2155,9 +2148,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 
	entry.fabricclk_mhz = 0;

	entry.fabricclk_mhz = 0;

	entry.dram_speed_mts = 0;

	entry.dram_speed_mts = 0;





	DC_FP_START();

	insert_entry_into_table_sorted(table, num_entries, &entry);

	insert_entry_into_table_sorted(table, num_entries, &entry);

	DC_FP_END();





	// Insert the UCLK DPMS

	// Insert the UCLK DPMS

	for (i = 0; i < num_uclk_dpms; i++) {

	for (i = 0; i < num_uclk_dpms; i++) {
@@ -2165,9 +2156,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 
		entry.fabricclk_mhz = 0;

		entry.fabricclk_mhz = 0;

		entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;

		entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;





		DC_FP_START();

		insert_entry_into_table_sorted(table, num_entries, &entry);

		insert_entry_into_table_sorted(table, num_entries, &entry);

		DC_FP_END();

	}

	}





	// If FCLK is coarse grained, insert individual DPMs.

	// If FCLK is coarse grained, insert individual DPMs.
@@ -2177,9 +2166,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 
			entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;

			entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;

			entry.dram_speed_mts = 0;

			entry.dram_speed_mts = 0;





			DC_FP_START();

			insert_entry_into_table_sorted(table, num_entries, &entry);

			insert_entry_into_table_sorted(table, num_entries, &entry);

			DC_FP_END();

		}

		}

	}

	}

	// If FCLK fine grained, only insert max

	// If FCLK fine grained, only insert max
@@ -2188,9 +2175,7 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 
		entry.fabricclk_mhz = max_fclk_mhz;

		entry.fabricclk_mhz = max_fclk_mhz;

		entry.dram_speed_mts = 0;

		entry.dram_speed_mts = 0;





		DC_FP_START();

		insert_entry_into_table_sorted(table, num_entries, &entry);

		insert_entry_into_table_sorted(table, num_entries, &entry);

		DC_FP_END();

	}

	}





	// At this point, the table contains all "points of interest" based on

	// At this point, the table contains all "points of interest" based on