Commit bc08fbf4 authored by Bjorn Andersson's avatar Bjorn Andersson
Browse files

arm64: dts: qcom: sm8350: Define GPI DMA engines 



The Qualcomm SM8350 has three GPI DMA engines, add definitions for
these.

Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: default avatarVinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20220412215137.2385831-1-bjorn.andersson@linaro.org
parent 97276cbf

arch/arm64/boot/dts/qcom/sm8350.dtsi

+73 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-sm8350.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/dma/qcom-gpi.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interconnect/qcom,sm8350.h>

#include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -675,6 +676,28 @@ opp-120000000 { 
			};

		};



		gpi_dma2: dma-controller@800000 {

			compatible = "qcom,sm8350-gpi-dma";

			reg = <0 0x00800000 0 0x60000>;

			interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;

			dma-channels = <12>;

			dma-channel-mask = <0xff>;

			iommus = <&apps_smmu 0x5f6 0x0>;

			#dma-cells = <3>;

			status = "disabled";

		};



		qupv3_id_2: geniqup@8c0000 {

			compatible = "qcom,geni-se-qup";

			reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -840,12 +863,37 @@ spi19: spi@894000 { 
				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;

				power-domains = <&rpmhpd SM8350_CX>;

				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,

				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;

				dma-names = "tx", "rx";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};

		};



		gpi_dma0: dma-controller@900000 {

			compatible = "qcom,sm8350-gpi-dma";

			reg = <0 0x09800000 0 0x60000>;

			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;

			dma-channels = <12>;

			dma-channel-mask = <0x7e>;

			iommus = <&apps_smmu 0x5b6 0x0>;

			#dma-cells = <3>;

			status = "disabled";

		};



		qupv3_id_0: geniqup@9c0000 {

			compatible = "qcom,geni-se-qup";

			reg = <0x0 0x009c0000 0x0 0x6000>;
@@ -1078,12 +1126,37 @@ spi7: spi@99c000 { 
				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;

				power-domains = <&rpmhpd SM8350_CX>;

				operating-points-v2 = <&qup_opp_table_100mhz>;

				dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,

				       <&gpi_dma0 1 7 QCOM_GPI_SPI>;

				dma-names = "tx", "rx";

				#address-cells = <1>;

				#size-cells = <0>;

				status = "disabled";

			};

		};



		gpi_dma1: dma-controller@a00000 {

			compatible = "qcom,sm8350-gpi-dma";

			reg = <0 0x00a00000 0 0x60000>;

			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;

			dma-channels = <12>;

			dma-channel-mask = <0xff>;

			iommus = <&apps_smmu 0x56 0x0>;

			#dma-cells = <3>;

			status = "disabled";

		};



		qupv3_id_1: geniqup@ac0000 {

			compatible = "qcom,geni-se-qup";

			reg = <0x0 0x00ac0000 0x0 0x6000>;