Commit bc872947 authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Vinod Koul
Browse files

soundwire: intel: move shim initialization before power up/down 



Move code around before additional simplification. No functionality
change.

Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarRander Wang <rander.wang@intel.com>
Signed-off-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20220919175721.354679-7-yung-chuan.liao@linux.intel.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent a658fd8d

drivers/soundwire/intel.c

+79 −80
Original line number Diff line number Diff line
@@ -260,86 +260,6 @@ static void intel_debugfs_exit(struct sdw_intel *sdw) {} 
/*

 * shim ops

 */



static int intel_link_power_up(struct sdw_intel *sdw)

{

	unsigned int link_id = sdw->instance;

	void __iomem *shim = sdw->link_res->shim;

	u32 *shim_mask = sdw->link_res->shim_mask;

	struct sdw_bus *bus = &sdw->cdns.bus;

	struct sdw_master_prop *prop = &bus->prop;

	u32 spa_mask, cpa_mask;

	u32 link_control;

	int ret = 0;

	u32 syncprd;

	u32 sync_reg;



	mutex_lock(sdw->link_res->shim_lock);



	/*

	 * The hardware relies on an internal counter, typically 4kHz,

	 * to generate the SoundWire SSP - which defines a 'safe'

	 * synchronization point between commands and audio transport

	 * and allows for multi link synchronization. The SYNCPRD value

	 * is only dependent on the oscillator clock provided to

	 * the IP, so adjust based on _DSD properties reported in DSDT

	 * tables. The values reported are based on either 24MHz

	 * (CNL/CML) or 38.4 MHz (ICL/TGL+).

	 */

	if (prop->mclk_freq % 6000000)

		syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;

	else

		syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;



	if (!*shim_mask) {

		dev_dbg(sdw->cdns.dev, "powering up all links\n");



		/* we first need to program the SyncPRD/CPU registers */

		dev_dbg(sdw->cdns.dev,

			"first link up, programming SYNCPRD\n");



		/* set SyncPRD period */

		sync_reg = intel_readl(shim, SDW_SHIM_SYNC);

		u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD);



		/* Set SyncCPU bit */

		sync_reg |= SDW_SHIM_SYNC_SYNCCPU;

		intel_writel(shim, SDW_SHIM_SYNC, sync_reg);



		/* Link power up sequence */

		link_control = intel_readl(shim, SDW_SHIM_LCTL);



		/* only power-up enabled links */

		spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask);

		cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);



		link_control |=  spa_mask;



		ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);

		if (ret < 0) {

			dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret);

			goto out;

		}



		/* SyncCPU will change once link is active */

		ret = intel_wait_bit(shim, SDW_SHIM_SYNC,

				     SDW_SHIM_SYNC_SYNCCPU, 0);

		if (ret < 0) {

			dev_err(sdw->cdns.dev,

				"Failed to set SHIM_SYNC: %d\n", ret);

			goto out;

		}

	}



	*shim_mask |= BIT(link_id);



	sdw->cdns.link_up = true;

out:

	mutex_unlock(sdw->link_res->shim_lock);



	return ret;

}



/* this needs to be called with shim_lock */

static void intel_shim_glue_to_master_ip(struct sdw_intel *sdw)

{
@@ -456,6 +376,85 @@ static void intel_shim_wake(struct sdw_intel *sdw, bool wake_enable) 
	mutex_unlock(sdw->link_res->shim_lock);

}



static int intel_link_power_up(struct sdw_intel *sdw)

{

	unsigned int link_id = sdw->instance;

	void __iomem *shim = sdw->link_res->shim;

	u32 *shim_mask = sdw->link_res->shim_mask;

	struct sdw_bus *bus = &sdw->cdns.bus;

	struct sdw_master_prop *prop = &bus->prop;

	u32 spa_mask, cpa_mask;

	u32 link_control;

	int ret = 0;

	u32 syncprd;

	u32 sync_reg;



	mutex_lock(sdw->link_res->shim_lock);



	/*

	 * The hardware relies on an internal counter, typically 4kHz,

	 * to generate the SoundWire SSP - which defines a 'safe'

	 * synchronization point between commands and audio transport

	 * and allows for multi link synchronization. The SYNCPRD value

	 * is only dependent on the oscillator clock provided to

	 * the IP, so adjust based on _DSD properties reported in DSDT

	 * tables. The values reported are based on either 24MHz

	 * (CNL/CML) or 38.4 MHz (ICL/TGL+).

	 */

	if (prop->mclk_freq % 6000000)

		syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_38_4;

	else

		syncprd = SDW_SHIM_SYNC_SYNCPRD_VAL_24;



	if (!*shim_mask) {

		dev_dbg(sdw->cdns.dev, "powering up all links\n");



		/* we first need to program the SyncPRD/CPU registers */

		dev_dbg(sdw->cdns.dev,

			"first link up, programming SYNCPRD\n");



		/* set SyncPRD period */

		sync_reg = intel_readl(shim, SDW_SHIM_SYNC);

		u32p_replace_bits(&sync_reg, syncprd, SDW_SHIM_SYNC_SYNCPRD);



		/* Set SyncCPU bit */

		sync_reg |= SDW_SHIM_SYNC_SYNCCPU;

		intel_writel(shim, SDW_SHIM_SYNC, sync_reg);



		/* Link power up sequence */

		link_control = intel_readl(shim, SDW_SHIM_LCTL);



		/* only power-up enabled links */

		spa_mask = FIELD_PREP(SDW_SHIM_LCTL_SPA_MASK, sdw->link_res->link_mask);

		cpa_mask = FIELD_PREP(SDW_SHIM_LCTL_CPA_MASK, sdw->link_res->link_mask);



		link_control |=  spa_mask;



		ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);

		if (ret < 0) {

			dev_err(sdw->cdns.dev, "Failed to power up link: %d\n", ret);

			goto out;

		}



		/* SyncCPU will change once link is active */

		ret = intel_wait_bit(shim, SDW_SHIM_SYNC,

				     SDW_SHIM_SYNC_SYNCCPU, 0);

		if (ret < 0) {

			dev_err(sdw->cdns.dev,

				"Failed to set SHIM_SYNC: %d\n", ret);

			goto out;

		}

	}



	*shim_mask |= BIT(link_id);



	sdw->cdns.link_up = true;

out:

	mutex_unlock(sdw->link_res->shim_lock);



	return ret;

}



static int intel_link_power_down(struct sdw_intel *sdw)

{

	u32 link_control, spa_mask, cpa_mask;