Commit bcd5e517 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r9a07g044: Add DMAC support 



Add DMAC support to RZ/G2L SoC DT.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719092535.4474-4-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent b8079550

arch/arm64/boot/dts/renesas/r9a07g044.dtsi

+36 −0
Original line number Diff line number Diff line
@@ -295,6 +295,42 @@ pinctrl: pin-controller@11030000 { 
				 <&cpg R9A07G044_GPIO_SPARE_RESETN>;

		};



		dmac: dma-controller@11820000 {

			compatible = "renesas,r9a07g044-dmac",

				     "renesas,rz-dmac";

			reg = <0 0x11820000 0 0x10000>,

			      <0 0x11830000 0 0x10000>;

			interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "error",

					  "ch0", "ch1", "ch2", "ch3",

					  "ch4", "ch5", "ch6", "ch7",

					  "ch8", "ch9", "ch10", "ch11",

					  "ch12", "ch13", "ch14", "ch15";

			clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,

				 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;

			power-domains = <&cpg>;

			resets = <&cpg R9A07G044_DMAC_ARESETN>,

				 <&cpg R9A07G044_DMAC_RST_ASYNC>;

			#dma-cells = <1>;

			dma-channels = <16>;

		};



		gic: interrupt-controller@11900000 {

			compatible = "arm,gic-v3";

			#interrupt-cells = <3>;