Commit bdfee324 authored by Andrzej Hajda's avatar Andrzej Hajda Committed by Jani Nikula
Browse files

drm/i915/display/phys: use intel_de_rmw if possible 



The helper makes the code more compact and readable.

Signed-off-by: default avatarAndrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230105131046.2173431-4-andrzej.hajda@intel.com
parent 98463a24

drivers/gpu/drm/i915/display/intel_combo_phy.c

+13 −30
Original line number Original line Diff line number Diff line
@@ -78,14 +78,11 @@ static void icl_set_procmon_ref_values(struct drm_i915_private *dev_priv, 
				       enum phy phy)

				       enum phy phy)

{

{

	const struct icl_procmon *procmon;

	const struct icl_procmon *procmon;

	u32 val;





	procmon = icl_get_procmon_ref_values(dev_priv, phy);

	procmon = icl_get_procmon_ref_values(dev_priv, phy);





	val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy));

	intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy),

	val &= ~((0xff << 16) | 0xff);

		     (0xff << 16) | 0xff, procmon->dw1);

	val |= procmon->dw1;

	intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val);





	intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9);

	intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9);

	intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10);

	intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10);
@@ -267,7 +264,6 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, 
				    int lane_count, bool lane_reversal)

				    int lane_count, bool lane_reversal)

{

{

	u8 lane_mask;

	u8 lane_mask;

	u32 val;





	if (is_dsi) {

	if (is_dsi) {

		drm_WARN_ON(&dev_priv->drm, lane_reversal);

		drm_WARN_ON(&dev_priv->drm, lane_reversal);
@@ -308,10 +304,8 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, 
		}

		}

	}

	}





	val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy));

	intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy),

	val &= ~PWR_DOWN_LN_MASK;

		     PWR_DOWN_LN_MASK, lane_mask);

	val |= lane_mask;

	intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val);

}

}





static void icl_combo_phys_init(struct drm_i915_private *dev_priv)

static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
@@ -366,19 +360,13 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) 




		icl_set_procmon_ref_values(dev_priv, phy);

		icl_set_procmon_ref_values(dev_priv, phy);





		if (phy_is_master(dev_priv, phy)) {

		if (phy_is_master(dev_priv, phy))

			val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy));

			intel_de_rmw(dev_priv, ICL_PORT_COMP_DW8(phy),

			val |= IREFGEN;

				     0, IREFGEN);

			intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val);

		}



		val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));

		val |= COMP_INIT;

		intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);





		val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));

		intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT);

		val |= CL_POWER_DOWN_ENABLE;

		intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),

		intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);

			     0, CL_POWER_DOWN_ENABLE);

	}

	}

}

}
@@ -387,8 +375,6 @@ static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) 
	enum phy phy;

	enum phy phy;





	for_each_combo_phy_reverse(dev_priv, phy) {

	for_each_combo_phy_reverse(dev_priv, phy) {

		u32 val;



		if (phy == PHY_A &&

		if (phy == PHY_A &&

		    !icl_combo_phy_verify_state(dev_priv, phy)) {

		    !icl_combo_phy_verify_state(dev_priv, phy)) {

			if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) {

			if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) {
@@ -410,14 +396,11 @@ static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) 
		if (!has_phy_misc(dev_priv, phy))

		if (!has_phy_misc(dev_priv, phy))

			goto skip_phy_misc;

			goto skip_phy_misc;





		val = intel_de_read(dev_priv, ICL_PHY_MISC(phy));

		intel_de_rmw(dev_priv, ICL_PHY_MISC(phy), 0,

		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;

			     ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN);

		intel_de_write(dev_priv, ICL_PHY_MISC(phy), val);





skip_phy_misc:

skip_phy_misc:

		val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy));

		intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0);

		val &= ~COMP_INIT;

		intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val);

	}

	}

}

}

drivers/gpu/drm/i915/display/intel_dpio_phy.c

+16 −35
Original line number Original line Diff line number Diff line
@@ -389,9 +389,7 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 
			"force reprogramming it\n", phy);

			"force reprogramming it\n", phy);

	}

	}





	val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);

	intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);

	val |= phy_info->pwron_mask;

	intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val);





	/*

	/*

	 * The PHY registers start out inaccessible and respond to reads with

	 * The PHY registers start out inaccessible and respond to reads with
@@ -410,27 +408,19 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 
			phy);

			phy);





	/* Program PLL Rcomp code offset */

	/* Program PLL Rcomp code offset */

	val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW9(phy));

	intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy), IREF0RC_OFFSET_MASK,

	val &= ~IREF0RC_OFFSET_MASK;

		     0xE4 << IREF0RC_OFFSET_SHIFT);

	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;

	intel_de_write(dev_priv, BXT_PORT_CL1CM_DW9(phy), val);





	val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW10(phy));

	intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy), IREF1RC_OFFSET_MASK,

	val &= ~IREF1RC_OFFSET_MASK;

		     0xE4 << IREF1RC_OFFSET_SHIFT);

	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;

	intel_de_write(dev_priv, BXT_PORT_CL1CM_DW10(phy), val);





	/* Program power gating */

	/* Program power gating */

	val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW28(phy));

	intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0,

	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |

		     OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG);

		SUS_CLK_CONFIG;

	intel_de_write(dev_priv, BXT_PORT_CL1CM_DW28(phy), val);





	if (phy_info->dual_channel) {

	if (phy_info->dual_channel)

		val = intel_de_read(dev_priv, BXT_PORT_CL2CM_DW6(phy));

		intel_de_rmw(dev_priv, BXT_PORT_CL2CM_DW6(phy), 0,

		val |= DW6_OLDO_DYN_PWR_DOWN_EN;

			     DW6_OLDO_DYN_PWR_DOWN_EN);

		intel_de_write(dev_priv, BXT_PORT_CL2CM_DW6(phy), val);

	}





	if (phy_info->rcomp_phy != -1) {

	if (phy_info->rcomp_phy != -1) {

		u32 grc_code;

		u32 grc_code;
@@ -449,34 +439,25 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 
			   val << GRC_CODE_SLOW_SHIFT |

			   val << GRC_CODE_SLOW_SHIFT |

			   val;

			   val;

		intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);

		intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);



		intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy),

		val = intel_de_read(dev_priv, BXT_PORT_REF_DW8(phy));

			     0, GRC_DIS | GRC_RDY_OVRD);

		val |= GRC_DIS | GRC_RDY_OVRD;

		intel_de_write(dev_priv, BXT_PORT_REF_DW8(phy), val);

	}

	}





	if (phy_info->reset_delay)

	if (phy_info->reset_delay)

		udelay(phy_info->reset_delay);

		udelay(phy_info->reset_delay);





	val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy));

	intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);

	val |= COMMON_RESET_DIS;

	intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val);

}

}





void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)

void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)

{

{

	const struct bxt_ddi_phy_info *phy_info;

	const struct bxt_ddi_phy_info *phy_info;

	u32 val;





	phy_info = bxt_get_phy_info(dev_priv, phy);

	phy_info = bxt_get_phy_info(dev_priv, phy);





	val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy));

	intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);

	val &= ~COMMON_RESET_DIS;

	intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val);





	val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);

	intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);

	val &= ~phy_info->pwron_mask;

	intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val);

}

}





void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)

void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)