Commit c18e99cf authored by Mike Frysinger's avatar Mike Frysinger Committed by Bryan Wu
Browse files

Blackfin arch: update anomaly sheets to match latest public info 



Signed-off-by: default avatarMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent ff19fed4

arch/blackfin/mach-bf518/include/mach/anomaly.h

+11 −2
Original line number Diff line number Diff line
@@ -2,12 +2,12 @@ 
 * File: include/asm-blackfin/mach-bf518/anomaly.h

 * Bugs: Enter bugs at http://blackfin.uclinux.org/

 *

 * Copyright (C) 2004-2008 Analog Devices Inc.

 * Copyright (C) 2004-2009 Analog Devices Inc.

 * Licensed under the GPL-2 or later.

 */



/* This file shoule be up to date with:

 *  - ????

 *  - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List

 */



#ifndef _MACH_ANOMALY_H_
@@ -19,6 +19,8 @@ 
#define ANOMALY_05000122 (1)

/* False Hardware Error from an Access in the Shadow of a Conditional Branch */

#define ANOMALY_05000245 (1)

/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */

#define ANOMALY_05000254 (1)

/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */

#define ANOMALY_05000265 (1)

/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
@@ -53,6 +55,12 @@ 
#define ANOMALY_05000443 (1)

/* Incorrect L1 Instruction Bank B Memory Map Location */

#define ANOMALY_05000444 (1)

/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */

#define ANOMALY_05000452 (1)

/* PWM_TRIPB Signal Not Available on PG10 */

#define ANOMALY_05000453 (1)

/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */

#define ANOMALY_05000455 (1)



/* Anomalies that don't exist on this proc */

#define ANOMALY_05000125 (0)
@@ -67,6 +75,7 @@ 
#define ANOMALY_05000273 (0)

#define ANOMALY_05000278 (0)

#define ANOMALY_05000285 (0)

#define ANOMALY_05000305 (0)

#define ANOMALY_05000307 (0)

#define ANOMALY_05000311 (0)

#define ANOMALY_05000312 (0)

arch/blackfin/mach-bf527/include/mach/anomaly.h

+2 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
 * File: include/asm-blackfin/mach-bf527/anomaly.h

 * Bugs: Enter bugs at http://blackfin.uclinux.org/

 *

 * Copyright (C) 2004-2008 Analog Devices Inc.

 * Copyright (C) 2004-2009 Analog Devices Inc.

 * Licensed under the GPL-2 or later.

 */
@@ -169,6 +169,7 @@ 
#define ANOMALY_05000273 (0)

#define ANOMALY_05000278 (0)

#define ANOMALY_05000285 (0)

#define ANOMALY_05000305 (0)

#define ANOMALY_05000307 (0)

#define ANOMALY_05000311 (0)

#define ANOMALY_05000312 (0)

arch/blackfin/mach-bf533/include/mach/anomaly.h

+2 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
 * File: include/asm-blackfin/mach-bf533/anomaly.h

 * Bugs: Enter bugs at http://blackfin.uclinux.org/

 *

 * Copyright (C) 2004-2008 Analog Devices Inc.

 * Copyright (C) 2004-2009 Analog Devices Inc.

 * Licensed under the GPL-2 or later.

 */
@@ -160,7 +160,7 @@ 
#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)

/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */

#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)

/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */

/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */

#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)

/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */

#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)

arch/blackfin/mach-bf537/include/mach/anomaly.h

+2 −2
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
 * File: include/asm-blackfin/mach-bf537/anomaly.h

 * Bugs: Enter bugs at http://blackfin.uclinux.org/

 *

 * Copyright (C) 2004-2008 Analog Devices Inc.

 * Copyright (C) 2004-2009 Analog Devices Inc.

 * Licensed under the GPL-2 or later.

 */
@@ -110,7 +110,7 @@ 
#define ANOMALY_05000301 (1)

/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */

#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)

/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */

/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */

#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)

/* SCKELOW Bit Does Not Maintain State Through Hibernate */

#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)

arch/blackfin/mach-bf538/include/mach/anomaly.h

+2 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
 * File: include/asm-blackfin/mach-bf538/anomaly.h

 * Bugs: Enter bugs at http://blackfin.uclinux.org/

 *

 * Copyright (C) 2004-2008 Analog Devices Inc.

 * Copyright (C) 2004-2009 Analog Devices Inc.

 * Licensed under the GPL-2 or later.

 */
@@ -120,6 +120,7 @@ 
#define ANOMALY_05000198 (0)

#define ANOMALY_05000230 (0)

#define ANOMALY_05000263 (0)

#define ANOMALY_05000305 (0)

#define ANOMALY_05000311 (0)

#define ANOMALY_05000323 (0)

#define ANOMALY_05000353 (1)