Loading drivers/net/sky2.c +5 −2 Original line number Diff line number Diff line Loading @@ -877,6 +877,10 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port) if (hw->dev[port]->mtu > ETH_DATA_LEN) reg |= GM_SMOD_JUMBO_ENA; if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_U_B1) reg |= GM_NEW_FLOW_CTRL; gma_write16(hw, port, GM_SERIAL_MODE, reg); /* virtual address for data */ Loading Loading @@ -1413,8 +1417,7 @@ static void sky2_rx_start(struct sky2_port *sky2) /* These chips have no ram buffer? * MAC Rx RAM Read is controlled by hardware */ if (hw->chip_id == CHIP_ID_YUKON_EC_U && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) hw->chip_rev > CHIP_REV_YU_EC_U_A0) sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); Loading drivers/net/sky2.h +8 −4 Original line number Diff line number Diff line Loading @@ -557,6 +557,7 @@ enum yukon_ec_u_rev { CHIP_REV_YU_EC_U_A0 = 1, CHIP_REV_YU_EC_U_A1 = 2, CHIP_REV_YU_EC_U_B0 = 3, CHIP_REV_YU_EC_U_B1 = 5, }; enum yukon_fe_rev { CHIP_REV_YU_FE_A1 = 1, Loading Loading @@ -1775,9 +1776,12 @@ enum { /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ enum { GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */ GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */ GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */ GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */ GM_SMOD_LIMIT_4 = 1<<10, /* 4 consecutive Tx trials */ GM_SMOD_VLAN_ENA = 1<<9, /* Enable VLAN (Max. Frame Len) */ GM_SMOD_JUMBO_ENA = 1<<8, /* Enable Jumbo (Max. Frame Len) */ GM_NEW_FLOW_CTRL = 1<<6, /* Enable New Flow-Control */ GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ }; Loading Loading
drivers/net/sky2.c +5 −2 Original line number Diff line number Diff line Loading @@ -877,6 +877,10 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port) if (hw->dev[port]->mtu > ETH_DATA_LEN) reg |= GM_SMOD_JUMBO_ENA; if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_U_B1) reg |= GM_NEW_FLOW_CTRL; gma_write16(hw, port, GM_SERIAL_MODE, reg); /* virtual address for data */ Loading Loading @@ -1413,8 +1417,7 @@ static void sky2_rx_start(struct sky2_port *sky2) /* These chips have no ram buffer? * MAC Rx RAM Read is controlled by hardware */ if (hw->chip_id == CHIP_ID_YUKON_EC_U && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) hw->chip_rev > CHIP_REV_YU_EC_U_A0) sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); Loading
drivers/net/sky2.h +8 −4 Original line number Diff line number Diff line Loading @@ -557,6 +557,7 @@ enum yukon_ec_u_rev { CHIP_REV_YU_EC_U_A0 = 1, CHIP_REV_YU_EC_U_A1 = 2, CHIP_REV_YU_EC_U_B0 = 3, CHIP_REV_YU_EC_U_B1 = 5, }; enum yukon_fe_rev { CHIP_REV_YU_FE_A1 = 1, Loading Loading @@ -1775,9 +1776,12 @@ enum { /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ enum { GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */ GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */ GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */ GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */ GM_SMOD_LIMIT_4 = 1<<10, /* 4 consecutive Tx trials */ GM_SMOD_VLAN_ENA = 1<<9, /* Enable VLAN (Max. Frame Len) */ GM_SMOD_JUMBO_ENA = 1<<8, /* Enable Jumbo (Max. Frame Len) */ GM_NEW_FLOW_CTRL = 1<<6, /* Enable New Flow-Control */ GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ }; Loading