Commit c3489214 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: dce 8 - 12 mem_input refactor to new style 



Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent aa7397df

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

+268 −38
Original line number Diff line number Diff line
@@ -23,18 +23,18 @@ 
 *

 */



#include "mem_input.h"

#include "dce_mem_input.h"

#include "reg_helper.h"

#include "basics/conversion.h"



#define CTX \

	mi->ctx

	dce_mi->base.ctx

#define REG(reg)\

	mi->regs->reg

	dce_mi->regs->reg



#undef FN

#define FN(reg_name, field_name) \

	mi->shifts->field_name, mi->masks->field_name

	dce_mi->shifts->field_name, dce_mi->masks->field_name



struct pte_setting {

	unsigned int bpp;
@@ -130,11 +130,13 @@ static bool is_vert_scan(enum dc_rotation_angle rotation) 
	}

}



void dce_mem_input_program_pte_vm(struct mem_input *mi,

static void dce_mi_program_pte_vm(

		struct mem_input *mi,

		enum surface_pixel_format format,

		union dc_tiling_info *tiling_info,

		enum dc_rotation_angle rotation)

{

	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);

	enum mi_bits_per_pixel mi_bpp = get_mi_bpp(format);

	enum mi_tiling_format mi_tiling = get_mi_tiling(tiling_info);

	const struct pte_setting *pte = &pte_settings[mi_tiling][mi_bpp];
@@ -158,7 +160,8 @@ void dce_mem_input_program_pte_vm(struct mem_input *mi, 
			DVMM_MAX_PTE_REQ_OUTSTANDING, 0xff);

}



static void program_urgency_watermark(struct mem_input *mi,

static void program_urgency_watermark(

	struct dce_mem_input *dce_mi,

	uint32_t wm_select,

	uint32_t urgency_low_wm,

	uint32_t urgency_high_wm)
@@ -171,7 +174,8 @@ static void program_urgency_watermark(struct mem_input *mi, 
		URGENCY_HIGH_WATERMARK, urgency_high_wm);

}



static void program_nbp_watermark(struct mem_input *mi,

static void program_nbp_watermark(

	struct dce_mem_input *dce_mi,

	uint32_t wm_select,

	uint32_t nbp_wm)

{
@@ -202,7 +206,8 @@ static void program_nbp_watermark(struct mem_input *mi, 
	}

}



static void program_stutter_watermark(struct mem_input *mi,

static void program_stutter_watermark(

	struct dce_mem_input *dce_mi,

	uint32_t wm_select,

	uint32_t stutter_mark)

{
@@ -217,41 +222,67 @@ static void program_stutter_watermark(struct mem_input *mi, 
				STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark);

}



void dce_mem_input_program_display_marks(struct mem_input *mi,

static void dce_mi_program_display_marks(

	struct mem_input *mi,

	struct dce_watermarks nbp,

	struct dce_watermarks stutter,

	struct dce_watermarks urgent,

	uint32_t total_dest_line_time_ns)

{

	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);

	uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;



	program_urgency_watermark(mi, 0, /* set a */

	program_urgency_watermark(dce_mi, 2, /* set a */

			urgent.a_mark, total_dest_line_time_ns);

	program_urgency_watermark(mi, 1, /* set b */

	program_urgency_watermark(dce_mi, 1, /* set d */

			urgent.d_mark, total_dest_line_time_ns);



	REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,

		STUTTER_ENABLE, stutter_en,

		STUTTER_IGNORE_FBC, 1);

	program_nbp_watermark(dce_mi, 2, nbp.a_mark); /* set a */

	program_nbp_watermark(dce_mi, 1, nbp.d_mark); /* set d */



	program_stutter_watermark(dce_mi, 2, stutter.a_mark); /* set a */

	program_stutter_watermark(dce_mi, 1, stutter.d_mark); /* set d */

}



static void dce120_mi_program_display_marks(struct mem_input *mi,

	struct dce_watermarks nbp,

	struct dce_watermarks stutter,

	struct dce_watermarks urgent,

	uint32_t total_dest_line_time_ns)

{

	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);

	uint32_t stutter_en = mi->ctx->dc->debug.disable_stutter ? 0 : 1;



	program_urgency_watermark(dce_mi, 0, /* set a */

			urgent.a_mark, total_dest_line_time_ns);

	program_urgency_watermark(dce_mi, 1, /* set b */

			urgent.b_mark, total_dest_line_time_ns);

	program_urgency_watermark(mi, 2, /* set c */

	program_urgency_watermark(dce_mi, 2, /* set c */

			urgent.c_mark, total_dest_line_time_ns);

	program_urgency_watermark(mi, 3, /* set d */

	program_urgency_watermark(dce_mi, 3, /* set d */

			urgent.d_mark, total_dest_line_time_ns);



	REG_UPDATE_2(DPG_PIPE_STUTTER_CONTROL,

		STUTTER_ENABLE, stutter_en,

		STUTTER_IGNORE_FBC, 1);

	program_nbp_watermark(mi, 0, nbp.a_mark); /* set a */

	program_nbp_watermark(mi, 1, nbp.b_mark); /* set b */

	program_nbp_watermark(mi, 2, nbp.c_mark); /* set c */

	program_nbp_watermark(mi, 3, nbp.d_mark); /* set d */



	program_stutter_watermark(mi, 0, stutter.a_mark); /* set a */

	program_stutter_watermark(mi, 1, stutter.b_mark); /* set b */

	program_stutter_watermark(mi, 2, stutter.c_mark); /* set c */

	program_stutter_watermark(mi, 3, stutter.d_mark); /* set d */

	program_nbp_watermark(dce_mi, 0, nbp.a_mark); /* set a */

	program_nbp_watermark(dce_mi, 1, nbp.b_mark); /* set b */

	program_nbp_watermark(dce_mi, 2, nbp.c_mark); /* set c */

	program_nbp_watermark(dce_mi, 3, nbp.d_mark); /* set d */



	program_stutter_watermark(dce_mi, 0, stutter.a_mark); /* set a */

	program_stutter_watermark(dce_mi, 1, stutter.b_mark); /* set b */

	program_stutter_watermark(dce_mi, 2, stutter.c_mark); /* set c */

	program_stutter_watermark(dce_mi, 3, stutter.d_mark); /* set d */

}



static void program_tiling(struct mem_input *mi,

	const union dc_tiling_info *info)

static void program_tiling(

	struct dce_mem_input *dce_mi, const union dc_tiling_info *info)

{

	if (mi->masks->GRPH_SW_MODE) { /* GFX9 */

	if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */

		REG_UPDATE_6(GRPH_CONTROL,

				GRPH_SW_MODE, info->gfx9.swizzle,

				GRPH_NUM_BANKS, log_2(info->gfx9.num_banks),
@@ -265,7 +296,7 @@ static void program_tiling(struct mem_input *mi, 
		 */

	}



	if (mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */

	if (dce_mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */

		REG_UPDATE_9(GRPH_CONTROL,

				GRPH_NUM_BANKS, info->gfx8.num_banks,

				GRPH_BANK_WIDTH, info->gfx8.bank_width,
@@ -285,7 +316,7 @@ static void program_tiling(struct mem_input *mi, 




static void program_size_and_rotation(

	struct mem_input *mi,

	struct dce_mem_input *dce_mi,

	enum dc_rotation_angle rotation,

	const union plane_size *plane_size)

{
@@ -326,7 +357,7 @@ static void program_size_and_rotation( 
}



static void program_grph_pixel_format(

	struct mem_input *mi,

	struct dce_mem_input *dce_mi,

	enum surface_pixel_format format)

{

	uint32_t red_xbar = 0, blue_xbar = 0; /* no swap */
@@ -397,7 +428,8 @@ static void program_grph_pixel_format( 
			GRPH_PRESCALE_B_SIGN, sign);

}



void dce_mem_input_program_surface_config(struct mem_input *mi,

static void dce_mi_program_surface_config(

	struct mem_input *mi,

	enum surface_pixel_format format,

	union dc_tiling_info *tiling_info,

	union plane_size *plane_size,
@@ -405,14 +437,15 @@ void dce_mem_input_program_surface_config(struct mem_input *mi, 
	struct dc_plane_dcc_param *dcc,

	bool horizontal_mirror)

{

	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);

	REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);



	program_tiling(mi, tiling_info);

	program_size_and_rotation(mi, rotation, plane_size);

	program_tiling(dce_mi, tiling_info);

	program_size_and_rotation(dce_mi, rotation, plane_size);



	if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&

		format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)

		program_grph_pixel_format(mi, format);

		program_grph_pixel_format(dce_mi, format);

}



static uint32_t get_dmif_switch_time_us(
@@ -461,12 +494,14 @@ static uint32_t get_dmif_switch_time_us( 
	return frame_time;

}



void dce_mem_input_allocate_dmif(struct mem_input *mi,

static void dce_mi_allocate_dmif(

	struct mem_input *mi,

	uint32_t h_total,

	uint32_t v_total,

	uint32_t pix_clk_khz,

	uint32_t total_stream_num)

{

	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);

	const uint32_t retry_delay = 10;

	uint32_t retry_count = get_dmif_switch_time_us(

			h_total,
@@ -497,18 +532,20 @@ void dce_mem_input_allocate_dmif(struct mem_input *mi, 
			PIXEL_DURATION, pix_dur);

	}



	if (mi->wa.single_head_rdreq_dmif_limit) {

	if (dce_mi->wa.single_head_rdreq_dmif_limit) {

		uint32_t eanble =  (total_stream_num > 1) ? 0 :

				mi->wa.single_head_rdreq_dmif_limit;

				dce_mi->wa.single_head_rdreq_dmif_limit;



		REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,

				ENABLE, eanble);

	}

}



void dce_mem_input_free_dmif(struct mem_input *mi,

static void dce_mi_free_dmif(

		struct mem_input *mi,

		uint32_t total_stream_num)

{

	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);

	uint32_t buffers_allocated;

	uint32_t dmif_buffer_control;
@@ -525,11 +562,204 @@ void dce_mem_input_free_dmif(struct mem_input *mi, 
			DMIF_BUFFERS_ALLOCATION_COMPLETED, 1,

			10, 3500);



	if (mi->wa.single_head_rdreq_dmif_limit) {

	if (dce_mi->wa.single_head_rdreq_dmif_limit) {

		uint32_t eanble =  (total_stream_num > 1) ? 0 :

				mi->wa.single_head_rdreq_dmif_limit;

				dce_mi->wa.single_head_rdreq_dmif_limit;



		REG_UPDATE(MC_HUB_RDREQ_DMIF_LIMIT,

				ENABLE, eanble);

	}

}





static void program_sec_addr(

	struct dce_mem_input *dce_mi,

	PHYSICAL_ADDRESS_LOC address)

{

	/*high register MUST be programmed first*/

	REG_SET(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0,

		GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,

		address.high_part);



	REG_SET_2(GRPH_SECONDARY_SURFACE_ADDRESS, 0,

		GRPH_SECONDARY_SURFACE_ADDRESS, address.low_part >> 8,

		GRPH_SECONDARY_DFQ_ENABLE, 0);

}



static void program_pri_addr(

	struct dce_mem_input *dce_mi,

	PHYSICAL_ADDRESS_LOC address)

{

	/*high register MUST be programmed first*/

	REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

		GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,

		address.high_part);



	REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS, 0,

		GRPH_PRIMARY_SURFACE_ADDRESS,

		address.low_part >> 8);

}





static bool dce_mi_is_flip_pending(struct mem_input *mem_input)

{

	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mem_input);

	uint32_t update_pending;



	REG_GET(GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, &update_pending);

	if (update_pending)

		return true;



	mem_input->current_address = mem_input->request_address;

	return false;

}



static bool dce_mi_program_surface_flip_and_addr(

	struct mem_input *mem_input,

	const struct dc_plane_address *address,

	bool flip_immediate)

{

	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mem_input);



	/* TODO: Figure out if two modes are needed:

	 * non-XDMA Mode: GRPH_SURFACE_UPDATE_IMMEDIATE_EN = 1

	 * XDMA Mode: GRPH_SURFACE_UPDATE_H_RETRACE_EN = 1

	 */

	REG_UPDATE(GRPH_UPDATE,

			GRPH_UPDATE_LOCK, 1);



	if (flip_immediate) {

		REG_UPDATE_2(GRPH_FLIP_CONTROL,

			GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,

			GRPH_SURFACE_UPDATE_H_RETRACE_EN, 1);

	} else {

		REG_UPDATE_2(GRPH_FLIP_CONTROL,

			GRPH_SURFACE_UPDATE_IMMEDIATE_EN, 0,

			GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);

	}



	switch (address->type) {

	case PLN_ADDR_TYPE_GRAPHICS:

		if (address->grph.addr.quad_part == 0)

			break;

		program_pri_addr(dce_mi, address->grph.addr);

		break;

	case PLN_ADDR_TYPE_GRPH_STEREO:

		if (address->grph_stereo.left_addr.quad_part == 0

			|| address->grph_stereo.right_addr.quad_part == 0)

			break;

		program_pri_addr(dce_mi, address->grph_stereo.left_addr);

		program_sec_addr(dce_mi, address->grph_stereo.right_addr);

		break;

	default:

		/* not supported */

		BREAK_TO_DEBUGGER();

		break;

	}



	mem_input->request_address = *address;



	if (flip_immediate)

		mem_input->current_address = *address;



	REG_UPDATE(GRPH_UPDATE,

			GRPH_UPDATE_LOCK, 0);



	return true;

}



static void dce_mi_update_dchub(struct mem_input *mi,

		struct dchub_init_data *dh_data)

{

	struct dce_mem_input *dce_mi = TO_DCE_MEM_INPUT(mi);

	/* TODO: port code from dal2 */

	switch (dh_data->fb_mode) {

	case FRAME_BUFFER_MODE_ZFB_ONLY:

		/*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/

		REG_UPDATE_2(DCHUB_FB_LOCATION,

				FB_TOP, 0,

				FB_BASE, 0x0FFFF);



		REG_UPDATE(DCHUB_AGP_BASE,

				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);



		REG_UPDATE(DCHUB_AGP_BOT,

				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);



		REG_UPDATE(DCHUB_AGP_TOP,

				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);

		break;

	case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:

		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/

		REG_UPDATE(DCHUB_AGP_BASE,

				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);



		REG_UPDATE(DCHUB_AGP_BOT,

				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);



		REG_UPDATE(DCHUB_AGP_TOP,

				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);

		break;

	case FRAME_BUFFER_MODE_LOCAL_ONLY:

		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/

		REG_UPDATE(DCHUB_AGP_BASE,

				AGP_BASE, 0);



		REG_UPDATE(DCHUB_AGP_BOT,

				AGP_BOT, 0x03FFFF);



		REG_UPDATE(DCHUB_AGP_TOP,

				AGP_TOP, 0);

		break;

	default:

		break;

	}



	dh_data->dchub_initialzied = true;

	dh_data->dchub_info_valid = false;

}



static struct mem_input_funcs dce_mi_funcs = {

	.mem_input_program_display_marks = dce_mi_program_display_marks,

	.allocate_mem_input = dce_mi_allocate_dmif,

	.free_mem_input = dce_mi_free_dmif,

	.mem_input_program_surface_flip_and_addr =

			dce_mi_program_surface_flip_and_addr,

	.mem_input_program_pte_vm = dce_mi_program_pte_vm,

	.mem_input_program_surface_config =

			dce_mi_program_surface_config,

	.mem_input_is_flip_pending = dce_mi_is_flip_pending,

	.mem_input_update_dchub = dce_mi_update_dchub

};





void dce_mem_input_construct(

	struct dce_mem_input *dce_mi,

	struct dc_context *ctx,

	int inst,

	const struct dce_mem_input_registers *regs,

	const struct dce_mem_input_shift *mi_shift,

	const struct dce_mem_input_mask *mi_mask)

{

	dce_mi->base.ctx = ctx;



	dce_mi->base.inst = inst;

	dce_mi->base.funcs = &dce_mi_funcs;



	dce_mi->regs = regs;

	dce_mi->shifts = mi_shift;

	dce_mi->masks = mi_mask;



}



void dce112_mem_input_construct(

	struct dce_mem_input *dce_mi,

	struct dc_context *ctx,

	int inst,

	const struct dce_mem_input_registers *regs,

	const struct dce_mem_input_shift *mi_shift,

	const struct dce_mem_input_mask *mi_mask)

{

	dce_mem_input_construct(dce_mi, ctx, inst, regs, mi_shift, mi_mask);

	dce_mi->base.funcs->mem_input_program_display_marks = dce120_mi_program_display_marks;

}

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

+83 −32
Original line number Diff line number Diff line
@@ -26,8 +26,10 @@ 
#define __DCE_MEM_INPUT_H__



#include "dc_hw_types.h"

struct dce_watermarks;

struct mem_input;

#include "mem_input.h"



#define TO_DCE_MEM_INPUT(mem_input)\

	container_of(mem_input, struct dce_mem_input, base)



#define MI_DCE_BASE_REG_LIST(id)\

	SRI(GRPH_ENABLE, DCP, id),\
@@ -40,6 +42,12 @@ struct mem_input; 
	SRI(HW_ROTATION, DCP, id),\

	SRI(GRPH_SWAP_CNTL, DCP, id),\

	SRI(PRESCALE_GRPH_CONTROL, DCP, id),\

	SRI(GRPH_UPDATE, DCP, id),\

	SRI(GRPH_FLIP_CONTROL, DCP, id),\

	SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\

	SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\

	SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\

	SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\

	SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\

	SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\

	SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\
@@ -67,7 +75,11 @@ struct mem_input; 
	MI_DCE_PTE_REG_LIST(id),\

	SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\

	SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\

	SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id)

	SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id),\

	SR(DCHUB_FB_LOCATION),\

	SR(DCHUB_AGP_BASE),\

	SR(DCHUB_AGP_BOT),\

	SR(DCHUB_AGP_TOP)



struct dce_mem_input_registers {

	/* DCP */
@@ -84,6 +96,12 @@ struct dce_mem_input_registers { 
	uint32_t GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT;

	uint32_t DVMM_PTE_CONTROL;

	uint32_t DVMM_PTE_ARB_CONTROL;

	uint32_t GRPH_UPDATE;

	uint32_t GRPH_FLIP_CONTROL;

	uint32_t GRPH_PRIMARY_SURFACE_ADDRESS;

	uint32_t GRPH_PRIMARY_SURFACE_ADDRESS_HIGH;

	uint32_t GRPH_SECONDARY_SURFACE_ADDRESS;

	uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH;

	/* DMIF_PG */

	uint32_t DPG_PIPE_ARBITRATION_CONTROL1;

	uint32_t DPG_WATERMARK_MASK_CONTROL;
@@ -96,6 +114,11 @@ struct dce_mem_input_registers { 
	uint32_t DMIF_BUFFER_CONTROL;

	/* MC_HUB */

	uint32_t MC_HUB_RDREQ_DMIF_LIMIT;

	/*DCHUB*/

	uint32_t DCHUB_FB_LOCATION;

	uint32_t DCHUB_AGP_BASE;

	uint32_t DCHUB_AGP_BOT;

	uint32_t DCHUB_AGP_TOP;

};



/* Set_Filed_for_Block */
@@ -129,9 +152,16 @@ struct dce_mem_input_registers { 
	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\

	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\

	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\

	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh)

	SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\

	SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\

	SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\

	SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\

	SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\

	SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\

	SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh)



#define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\

	SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_IMMEDIATE_EN, mask_sh),\

	SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh)



#define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk)\
@@ -189,13 +219,22 @@ struct dce_mem_input_registers { 
	SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\

	SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh)



#define MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\

	SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\

	SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\

	SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\

	SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\

	SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh)



#define MI_DCE12_MASK_SH_LIST(mask_sh)\

	MI_DCP_MASK_SH_LIST(mask_sh, DCP0_),\

	SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\

	MI_DCP_DCE11_MASK_SH_LIST(mask_sh, DCP0_),\

	MI_DCP_PTE_MASK_SH_LIST(mask_sh, DCP0_),\

	MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\

	MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\

	MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_)

	MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_),\

	MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)



#define MI_REG_FIELD_LIST(type) \

	type GRPH_ENABLE; \
@@ -232,6 +271,15 @@ struct dce_mem_input_registers { 
	type GRPH_SE_ENABLE; \

	type GRPH_NUM_SHADER_ENGINES; \

	type GRPH_NUM_PIPES; \

	type GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; \

	type GRPH_SECONDARY_SURFACE_ADDRESS; \

	type GRPH_SECONDARY_DFQ_ENABLE; \

	type GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; \

	type GRPH_PRIMARY_SURFACE_ADDRESS; \

	type GRPH_SURFACE_UPDATE_PENDING; \

	type GRPH_SURFACE_UPDATE_IMMEDIATE_EN; \

	type GRPH_SURFACE_UPDATE_H_RETRACE_EN; \

	type GRPH_UPDATE_LOCK; \

	type PIXEL_DURATION; \

	type URGENCY_WATERMARK_MASK; \

	type PSTATE_CHANGE_WATERMARK_MASK; \
@@ -253,6 +301,11 @@ struct dce_mem_input_registers { 
	type DMIF_BUFFERS_ALLOCATED; \

	type DMIF_BUFFERS_ALLOCATION_COMPLETED; \

	type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\

	type FB_BASE; \

	type FB_TOP; \

	type AGP_BASE; \

	type AGP_TOP; \

	type AGP_BOT; \



struct dce_mem_input_shift {

	MI_REG_FIELD_LIST(uint8_t)
@@ -266,32 +319,30 @@ struct dce_mem_input_wa { 
	uint8_t single_head_rdreq_dmif_limit;

};



void dce_mem_input_program_pte_vm(struct mem_input *mi,

	enum surface_pixel_format format,

	union dc_tiling_info *tiling_info,

	enum dc_rotation_angle rotation);



void dce_mem_input_program_surface_config(struct mem_input *mi,

	enum surface_pixel_format format,

	union dc_tiling_info *tiling_info,

	union plane_size *plane_size,

	enum dc_rotation_angle rotation,

	struct dc_plane_dcc_param *dcc,

	bool horizontal_mirror);



void dce_mem_input_allocate_dmif(struct mem_input *mi,

	uint32_t h_total,

	uint32_t v_total,

	uint32_t pix_clk_khz,

	uint32_t total_stream_num);



void dce_mem_input_free_dmif(struct mem_input *mi,

	uint32_t total_stream_num);



void dce_mem_input_program_display_marks(struct mem_input *mi,

	struct dce_watermarks nbp,

	struct dce_watermarks stutter,

	struct dce_watermarks urgent,

	uint32_t total_dest_line_time_ns);

struct dce_mem_input {

	struct mem_input base;



	const struct dce_mem_input_registers *regs;

	const struct dce_mem_input_shift *shifts;

	const struct dce_mem_input_mask *masks;



	struct dce_mem_input_wa wa;

};



void dce_mem_input_construct(

	struct dce_mem_input *dce_mi,

	struct dc_context *ctx,

	int inst,

	const struct dce_mem_input_registers *regs,

	const struct dce_mem_input_shift *mi_shift,

	const struct dce_mem_input_mask *mi_mask);



void dce112_mem_input_construct(

	struct dce_mem_input *dce_mi,

	struct dc_context *ctx,

	int inst,

	const struct dce_mem_input_registers *regs,

	const struct dce_mem_input_shift *mi_shift,

	const struct dce_mem_input_mask *mi_mask);



#endif /*__DCE_MEM_INPUT_H__*/

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

+11 −67
Original line number Diff line number Diff line
@@ -35,8 +35,8 @@ 
#include "irq/dce110/irq_service_dce110.h"

#include "dce/dce_link_encoder.h"

#include "dce/dce_stream_encoder.h"

#include "dce110/dce110_mem_input.h"

#include "dce110/dce110_mem_input_v.h"



#include "dce/dce_mem_input.h"

#include "dce/dce_ipp.h"

#include "dce/dce_transform.h"

#include "dce/dce_opp.h"
@@ -123,51 +123,6 @@ static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = { 
	}

};



static const struct dce110_mem_input_reg_offsets dce100_mi_reg_offsets[] = {

	{

		.dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),

		.dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL

				- mmDPG_WATERMARK_MASK_CONTROL),

		.pipe = (mmPIPE0_DMIF_BUFFER_CONTROL

				- mmPIPE0_DMIF_BUFFER_CONTROL),

	},

	{

		.dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),

		.dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL

				- mmDPG_WATERMARK_MASK_CONTROL),

		.pipe = (mmPIPE1_DMIF_BUFFER_CONTROL

				- mmPIPE0_DMIF_BUFFER_CONTROL),

	},

	{

		.dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),

		.dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL

				- mmDPG_WATERMARK_MASK_CONTROL),

		.pipe = (mmPIPE2_DMIF_BUFFER_CONTROL

				- mmPIPE0_DMIF_BUFFER_CONTROL),

	},

	{

		.dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),

		.dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL

				- mmDPG_WATERMARK_MASK_CONTROL),

		.pipe = (mmPIPE3_DMIF_BUFFER_CONTROL

				- mmPIPE0_DMIF_BUFFER_CONTROL),

	},

	{

		.dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),

		.dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL

				- mmDPG_WATERMARK_MASK_CONTROL),

		.pipe = (mmPIPE4_DMIF_BUFFER_CONTROL

				- mmPIPE0_DMIF_BUFFER_CONTROL),

	},

	{

		.dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),

		.dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL

				- mmDPG_WATERMARK_MASK_CONTROL),

		.pipe = (mmPIPE5_DMIF_BUFFER_CONTROL

				- mmPIPE0_DMIF_BUFFER_CONTROL),

	}

};



/* set register offset */

#define SR(reg_name)\

	.reg_name = mm ## reg_name
@@ -510,28 +465,18 @@ static const struct dce_mem_input_mask mi_masks = { 


static struct mem_input *dce100_mem_input_create(

	struct dc_context *ctx,

	uint32_t inst,

	const struct dce110_mem_input_reg_offsets *offset)

	uint32_t inst)

{

	struct dce110_mem_input *mem_input110 =

		dm_alloc(sizeof(struct dce110_mem_input));

	struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input));



	if (!mem_input110)

	if (!dce_mi) {

		BREAK_TO_DEBUGGER();

		return NULL;



	if (dce110_mem_input_construct(mem_input110, ctx, inst, offset)) {

		struct mem_input *mi = &mem_input110->base;



		mi->regs = &mi_regs[inst];

		mi->shifts = &mi_shifts;

		mi->masks = &mi_masks;

		mi->wa.single_head_rdreq_dmif_limit = 2;

		return mi;

	}



	BREAK_TO_DEBUGGER();

	dm_free(mem_input110);

	return NULL;

	dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);

	dce_mi->wa.single_head_rdreq_dmif_limit = 2;

	return &dce_mi->base;

}



static void dce100_transform_destroy(struct transform **xfm)
@@ -671,7 +616,7 @@ static void destruct(struct dce110_resource_pool *pool) 
			dce_ipp_destroy(&pool->base.ipps[i]);



		if (pool->base.mis[i] != NULL) {

			dm_free(TO_DCE110_MEM_INPUT(pool->base.mis[i]));

			dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i]));

			pool->base.mis[i] = NULL;

		}
@@ -986,8 +931,7 @@ static bool construct( 
			goto res_create_fail;

		}



		pool->base.mis[i] = dce100_mem_input_create(ctx, i,

				&dce100_mi_reg_offsets[i]);

		pool->base.mis[i] = dce100_mem_input_create(ctx, i);

		if (pool->base.mis[i] == NULL) {

			BREAK_TO_DEBUGGER();

			dm_error(

drivers/gpu/drm/amd/display/dc/dce110/Makefile

+1 −2
Original line number Diff line number Diff line
@@ -3,8 +3,7 @@ 
# It provides the control and status of HW CRTC block.



DCE110 = dce110_timing_generator.o \

dce110_compressor.o dce110_mem_input.o dce110_hw_sequencer.o \

dce110_resource.o \

dce110_compressor.o dce110_hw_sequencer.o dce110_resource.o \

dce110_opp_regamma_v.o dce110_opp_csc_v.o dce110_timing_generator_v.o \

dce110_mem_input_v.o dce110_opp_v.o dce110_transform_v.o

drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c

deleted100644 → 0
+0 −437

File deleted.

Preview size limit exceeded, changes collapsed.