Unverified Commit c39e299a authored by Mark Brown's avatar Mark Brown
Browse files

ASoC: codecs: jz4725b: Various improvements and fixes 

Merge series from Siarhei Volkau <lis8215@gmail.com>:

The patchset fixes:
 - Line In path stays powered off during capturing or
   bypass to mixer.
 - incorrectly represented dB values in alsamixer, et al.
 - incorrect represented Capture input selector in alsamixer
   in Playback tab.
 - wrong control selected as Capture Master

The patchset improves:
 - Exposes output stage (post mixer) gain control and makes it new
   Master playback gain, DAC gain was the previous master.
   However, no Master mute now.
 - Exposes all mixer inputs (both Mics, LineIn and DAC) with their
   gain controls.
 - Exposes microphones widgets: single/differential input, boost.

Known issues:
 - Bypass path enablement isn't applied immediately, for make
   things going bit clock needs to be triggered for a bit,
   e.g. by aplay dummy.wav
   It might be a hardware bug, since the bit clock isn't
   declared as required for codec operation.

Tested on:
 - Ritmix RZX-27 (jz4725b).
 - Ritmix RZX-50 (jz4755).
parents 67ad4edf 4b192aa0

sound/soc/codecs/jz4725b.c

+92 −17
Original line number Diff line number Diff line
@@ -136,28 +136,89 @@ enum { 
#define REG_CGR3_GO1L_OFFSET		0

#define REG_CGR3_GO1L_MASK		(0x1f << REG_CGR3_GO1L_OFFSET)



#define REG_CGR4_GO2R_OFFSET		0

#define REG_CGR4_GO2R_MASK		(0x1f << REG_CGR4_GO2R_OFFSET)



#define REG_CGR5_GO2L_OFFSET		0

#define REG_CGR5_GO2L_MASK		(0x1f << REG_CGR5_GO2L_OFFSET)



#define REG_CGR6_GO3R_OFFSET		0

#define REG_CGR6_GO3R_MASK		(0x1f << REG_CGR6_GO3R_OFFSET)



#define REG_CGR7_GO3L_OFFSET		0

#define REG_CGR7_GO3L_MASK		(0x1f << REG_CGR7_GO3L_OFFSET)



#define REG_CGR8_GOR_OFFSET		0

#define REG_CGR8_GOR_MASK		(0x1f << REG_CGR8_GOR_OFFSET)



#define REG_CGR9_GOL_OFFSET		0

#define REG_CGR9_GOL_MASK		(0x1f << REG_CGR9_GOL_OFFSET)



#define REG_CGR10_GIL_OFFSET		0

#define REG_CGR10_GIR_OFFSET		4



struct jz_icdc {

	struct regmap *regmap;

	void __iomem *base;

	struct clk *clk;

};



static const SNDRV_CTL_TLVD_DECLARE_DB_LINEAR(jz4725b_dac_tlv, -2250, 0);

static const SNDRV_CTL_TLVD_DECLARE_DB_LINEAR(jz4725b_line_tlv, -1500, 600);

static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_adc_tlv,     0, 150, 0);

static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_dac_tlv, -2250, 150, 0);

static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(jz4725b_mix_tlv,

	 0, 11, TLV_DB_SCALE_ITEM(-2250,   0, 0),

	12, 31, TLV_DB_SCALE_ITEM(-2250, 150, 0),

);



static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(jz4725b_out_tlv,

	 0, 11, TLV_DB_SCALE_ITEM(-3350, 200, 0),

	12, 23, TLV_DB_SCALE_ITEM(-1050, 100, 0),

	24, 31, TLV_DB_SCALE_ITEM(  100,  50, 0),

);

static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(jz4725b_mic_boost_tlv, 0, 2000, 0);



static const char * const jz4725b_mic_mode_texts[] = {

	"Single Ended", "Differential",

};



static const struct soc_enum jz4725b_mic_mode_enum =

	SOC_ENUM_SINGLE(JZ4725B_CODEC_REG_CR3, REG_CR3_MICDIFF_OFFSET,

			2, jz4725b_mic_mode_texts);



static const struct snd_kcontrol_new jz4725b_codec_controls[] = {

	SOC_DOUBLE_TLV("Master Playback Volume",

	SOC_DOUBLE_TLV("DAC Playback Volume",

		       JZ4725B_CODEC_REG_CGR1,

		       REG_CGR1_GODL_OFFSET,

		       REG_CGR1_GODR_OFFSET,

		       0xf, 1, jz4725b_dac_tlv),

	SOC_DOUBLE_R_TLV("Master Capture Volume",

	SOC_DOUBLE_TLV("Master Capture Volume",

		       JZ4725B_CODEC_REG_CGR10,

		       REG_CGR10_GIL_OFFSET,

		       REG_CGR10_GIR_OFFSET,

		       0xf, 0, jz4725b_adc_tlv),

	SOC_DOUBLE_R_TLV("Mixer Line In Bypass Playback Volume",

			 JZ4725B_CODEC_REG_CGR3,

			 JZ4725B_CODEC_REG_CGR2,

			 REG_CGR2_GO1R_OFFSET,

			 0x1f, 1, jz4725b_line_tlv),

			 0x1f, 1, jz4725b_mix_tlv),

	SOC_DOUBLE_R_TLV("Mixer Mic 1 Bypass Playback Volume",

			 JZ4725B_CODEC_REG_CGR5,

			 JZ4725B_CODEC_REG_CGR4,

			 REG_CGR4_GO2R_OFFSET,

			 0x1f, 1, jz4725b_mix_tlv),

	SOC_DOUBLE_R_TLV("Mixer Mic 2 Bypass Playback Volume",

			 JZ4725B_CODEC_REG_CGR7,

			 JZ4725B_CODEC_REG_CGR6,

			 REG_CGR6_GO3R_OFFSET,

			 0x1f, 1, jz4725b_mix_tlv),



	SOC_DOUBLE_R_TLV("Master Playback Volume",

			 JZ4725B_CODEC_REG_CGR9,

			 JZ4725B_CODEC_REG_CGR8,

			 REG_CGR8_GOR_OFFSET,

			 0x1f, 1, jz4725b_out_tlv),



	SOC_SINGLE("Master Playback Switch", JZ4725B_CODEC_REG_CR1,

	SOC_SINGLE("DAC Playback Switch", JZ4725B_CODEC_REG_CR1,

		   REG_CR1_DAC_MUTE_OFFSET, 1, 1),



	SOC_SINGLE("Deemphasize Filter Playback Switch",
@@ -167,6 +228,13 @@ static const struct snd_kcontrol_new jz4725b_codec_controls[] = { 
	SOC_SINGLE("High-Pass Filter Capture Switch",

		   JZ4725B_CODEC_REG_CR2,

		   REG_CR2_ADC_HPF_OFFSET, 1, 0),



	SOC_ENUM("Mic Mode Capture Switch", jz4725b_mic_mode_enum),



	SOC_SINGLE_TLV("Mic1 Boost Capture Volume",

		       JZ4725B_CODEC_REG_PMR2,

		       REG_PMR2_GIM_OFFSET,

		       1, 0, jz4725b_mic_boost_tlv),

};



static const char * const jz4725b_codec_adc_src_texts[] = {
@@ -180,11 +248,15 @@ static SOC_VALUE_ENUM_SINGLE_DECL(jz4725b_codec_adc_src_enum, 
				  jz4725b_codec_adc_src_texts,

				  jz4725b_codec_adc_src_values);

static const struct snd_kcontrol_new jz4725b_codec_adc_src_ctrl =

			SOC_DAPM_ENUM("Route", jz4725b_codec_adc_src_enum);

	SOC_DAPM_ENUM("ADC Source Capture Route", jz4725b_codec_adc_src_enum);



static const struct snd_kcontrol_new jz4725b_codec_mixer_controls[] = {

	SOC_DAPM_SINGLE("Line In Bypass", JZ4725B_CODEC_REG_CR1,

	SOC_DAPM_SINGLE("Line In Bypass Playback Switch", JZ4725B_CODEC_REG_CR1,

			REG_CR1_BYPASS_OFFSET, 1, 0),

	SOC_DAPM_SINGLE("Mic 1 Bypass Playback Switch", JZ4725B_CODEC_REG_CR3,

			REG_CR3_SIDETONE1_OFFSET, 1, 0),

	SOC_DAPM_SINGLE("Mic 2 Bypass Playback Switch", JZ4725B_CODEC_REG_CR3,

			REG_CR3_SIDETONE2_OFFSET, 1, 0),

};



static int jz4725b_out_stage_enable(struct snd_soc_dapm_widget *w,
@@ -225,7 +297,7 @@ static const struct snd_soc_dapm_widget jz4725b_codec_dapm_widgets[] = { 
	SND_SOC_DAPM_ADC("ADC", "Capture",

			 JZ4725B_CODEC_REG_PMR1, REG_PMR1_SB_ADC_OFFSET, 1),



	SND_SOC_DAPM_MUX("ADC Source", SND_SOC_NOPM, 0, 0,

	SND_SOC_DAPM_MUX("ADC Source Capture Route", SND_SOC_NOPM, 0, 0,

			 &jz4725b_codec_adc_src_ctrl),



	/* Mixer */
@@ -236,7 +308,8 @@ static const struct snd_soc_dapm_widget jz4725b_codec_dapm_widgets[] = { 
	SND_SOC_DAPM_MIXER("DAC to Mixer", JZ4725B_CODEC_REG_CR1,

			   REG_CR1_DACSEL_OFFSET, 0, NULL, 0),



	SND_SOC_DAPM_MIXER("Line In", SND_SOC_NOPM, 0, 0, NULL, 0),

	SND_SOC_DAPM_MIXER("Line In", JZ4725B_CODEC_REG_PMR1,

			   REG_PMR1_SB_LIN_OFFSET, 1, NULL, 0),

	SND_SOC_DAPM_MIXER("HP Out", JZ4725B_CODEC_REG_CR1,

			   REG_CR1_HP_DIS_OFFSET, 1, NULL, 0),
@@ -278,16 +351,18 @@ static const struct snd_soc_dapm_route jz4725b_codec_dapm_routes[] = { 
	{"Line In", NULL, "LLINEIN"},

	{"Line In", NULL, "RLINEIN"},



	{"Mixer", "Line In Bypass", "Line In"},

	{"Mixer", "Mic 1 Bypass Playback Switch", "Mic 1"},

	{"Mixer", "Mic 2 Bypass Playback Switch", "Mic 2"},

	{"Mixer", "Line In Bypass Playback Switch", "Line In"},

	{"DAC to Mixer", NULL, "DAC"},

	{"Mixer", NULL, "DAC to Mixer"},



	{"Mixer to ADC", NULL, "Mixer"},

	{"ADC Source", "Mixer", "Mixer to ADC"},

	{"ADC Source", "Line In", "Line In"},

	{"ADC Source", "Mic 1", "Mic 1"},

	{"ADC Source", "Mic 2", "Mic 2"},

	{"ADC", NULL, "ADC Source"},

	{"ADC Source Capture Route", "Mixer", "Mixer to ADC"},

	{"ADC Sourc Capture Routee", "Line In", "Line In"},

	{"ADC Source Capture Route", "Mic 1", "Mic 1"},

	{"ADC Source Capture Route", "Mic 2", "Mic 2"},

	{"ADC", NULL, "ADC Source Capture Route"},



	{"Out Stage", NULL, "Mixer"},

	{"HP Out", NULL, "Out Stage"},