Commit c606c2fd authored by Kuninori Morimoto's avatar Kuninori Morimoto Committed by Geert Uytterhoeven
Browse files

pinctrl: renesas: r8a779g0: Add missing PWM 



R-Car V4H has PWM/PWM_A/PWM_B, but current PFC setting is mixed.
This patch adds missing PWM settings, and tidies these up.

According to Document, GP3_14 Function4 is PWM2_A,
but we can't select it at P1SR3[27:24].
This patch just ignore it for now.

Signed-off-by: default avatarKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87o7y9sj90.wl-kuninori.morimoto.gx@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 1c2646b5

drivers/pinctrl/renesas/pfc-r8a779g0.c

+84 −56
Original line number Diff line number Diff line
@@ -310,9 +310,9 @@ 
#define IP1SR1_11_8	FM(MSIOF0_SCK)		FM(HSCK1_X)		FM(SCK1_X)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR1_15_12	FM(MSIOF0_RXD)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR1_19_16	FM(HTX0)		FM(TX0)			F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR1_23_20	FM(HCTS0_N)		FM(CTS0_N)		FM(PWM8)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR1_27_24	FM(HRTS0_N)		FM(RTS0_N)		FM(PWM9)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR1_31_28	FM(HSCK0)		FM(SCK0)		FM(PWM0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR1_23_20	FM(HCTS0_N)		FM(CTS0_N)		FM(PWM8_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR1_27_24	FM(HRTS0_N)		FM(RTS0_N)		FM(PWM9_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR1_31_28	FM(HSCK0)		FM(SCK0)		FM(PWM0_A)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)



/* IP2SR1 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */

#define IP2SR1_3_0	FM(HRX0)		FM(RX0)			F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -321,7 +321,7 @@ 
#define IP2SR1_15_12	FM(SSI_WS)		FM(TCLK4)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP2SR1_19_16	FM(SSI_SD)		FM(IRQ0_A)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP2SR1_23_20	FM(AUDIO_CLKOUT)	FM(IRQ1_A)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP2SR1_27_24	FM(AUDIO_CLKIN)		FM(PWM3)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP2SR1_27_24	FM(AUDIO_CLKIN)		FM(PWM3_A)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP2SR1_31_28	F_(0, 0)		FM(TCLK2)		FM(MSIOF4_SS1)	FM(IRQ3_B)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)



/* IP3SR1 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
@@ -348,9 +348,9 @@ 
#define IP1SR2_11_8	FM(CANFD0_TX)		FM(FXR_TXENB_N_X)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR2_15_12	FM(CANFD0_RX)		FM(STPWT_EXTFXR)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR2_19_16	FM(CANFD2_TX)		FM(TPU0TO2)		F_(0, 0)	FM(TCLK3_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR2_23_20	FM(CANFD2_RX)		FM(TPU0TO3)		FM(PWM1)	FM(TCLK4_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR2_27_24	FM(CANFD3_TX)		F_(0, 0)		FM(PWM2)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR2_31_28	FM(CANFD3_RX)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR2_23_20	FM(CANFD2_RX)		FM(TPU0TO3)		FM(PWM1_B)	FM(TCLK4_A)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR2_27_24	FM(CANFD3_TX)		F_(0, 0)		FM(PWM2_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR2_31_28	FM(CANFD3_RX)		F_(0, 0)		FM(PWM3_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)



/* IP2SR2 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */

#define IP2SR2_3_0	FM(CANFD4_TX)		F_(0, 0)		FM(PWM4)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -375,7 +375,7 @@ 
#define IP1SR3_11_8	FM(MMC_SD_CMD)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR3_15_12	FM(SD_CD)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR3_19_16	FM(SD_WP)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR3_23_20	FM(IPC_CLKIN)		FM(IPC_CLKEN_IN)	F_(0, 0)	FM(TCLK3_X)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR3_23_20	FM(IPC_CLKIN)		FM(IPC_CLKEN_IN)	FM(PWM1_A)	FM(TCLK3_X)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR3_27_24	FM(IPC_CLKOUT)		FM(IPC_CLKEN_OUT)	F_(0, 0)	FM(TCLK4_X)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP1SR3_31_28	FM(QSPI0_SSL)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -845,15 +845,15 @@ static const u16 pinmux_data[] = { 


	PINMUX_IPSR_GPSR(IP1SR1_23_20,	HCTS0_N),

	PINMUX_IPSR_GPSR(IP1SR1_23_20,	CTS0_N),

	PINMUX_IPSR_GPSR(IP1SR1_23_20,	PWM8),

	PINMUX_IPSR_GPSR(IP1SR1_23_20,	PWM8_A),



	PINMUX_IPSR_GPSR(IP1SR1_27_24,	HRTS0_N),

	PINMUX_IPSR_GPSR(IP1SR1_27_24,	RTS0_N),

	PINMUX_IPSR_GPSR(IP1SR1_27_24,	PWM9),

	PINMUX_IPSR_GPSR(IP1SR1_27_24,	PWM9_A),



	PINMUX_IPSR_GPSR(IP1SR1_31_28,	HSCK0),

	PINMUX_IPSR_GPSR(IP1SR1_31_28,	SCK0),

	PINMUX_IPSR_GPSR(IP1SR1_31_28,	PWM0),

	PINMUX_IPSR_GPSR(IP1SR1_31_28,	PWM0_A),



	/* IP2SR1 */

	PINMUX_IPSR_GPSR(IP2SR1_3_0,	HRX0),
@@ -875,7 +875,7 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_GPSR(IP2SR1_23_20,	IRQ1_A),



	PINMUX_IPSR_GPSR(IP2SR1_27_24,	AUDIO_CLKIN),

	PINMUX_IPSR_GPSR(IP2SR1_27_24,	PWM3),

	PINMUX_IPSR_GPSR(IP2SR1_27_24,	PWM3_A),



	PINMUX_IPSR_GPSR(IP2SR1_31_28,	TCLK2),

	PINMUX_IPSR_GPSR(IP2SR1_31_28,	MSIOF4_SS1),
@@ -951,13 +951,14 @@ static const u16 pinmux_data[] = { 


	PINMUX_IPSR_GPSR(IP1SR2_23_20,	CANFD2_RX),

	PINMUX_IPSR_GPSR(IP1SR2_23_20,	TPU0TO3),

	PINMUX_IPSR_GPSR(IP1SR2_23_20,	PWM1),

	PINMUX_IPSR_GPSR(IP1SR2_23_20,	PWM1_B),

	PINMUX_IPSR_GPSR(IP1SR2_23_20,	TCLK4_A),



	PINMUX_IPSR_GPSR(IP1SR2_27_24,	CANFD3_TX),

	PINMUX_IPSR_GPSR(IP1SR2_27_24,	PWM2),

	PINMUX_IPSR_GPSR(IP1SR2_27_24,	PWM2_B),



	PINMUX_IPSR_GPSR(IP1SR2_31_28,	CANFD3_RX),

	PINMUX_IPSR_GPSR(IP1SR2_31_28,	PWM3_B),



	/* IP2SR2 */

	PINMUX_IPSR_GPSR(IP2SR2_3_0,	CANFD4_TX),
@@ -995,6 +996,7 @@ static const u16 pinmux_data[] = { 


	PINMUX_IPSR_GPSR(IP1SR3_23_20,	IPC_CLKIN),

	PINMUX_IPSR_GPSR(IP1SR3_23_20,	IPC_CLKEN_IN),

	PINMUX_IPSR_GPSR(IP1SR3_23_20,	PWM1_A),

	PINMUX_IPSR_GPSR(IP1SR3_23_20,	TCLK3_X),



	PINMUX_IPSR_GPSR(IP1SR3_27_24,	IPC_CLKOUT),
@@ -2030,40 +2032,58 @@ static const unsigned int pcie1_clkreq_n_mux[] = { 
	PCIE1_CLKREQ_N_MARK,

};



/* - PWM0 ------------------------------------------------------------------- */

static const unsigned int pwm0_pins[] = {

	/* PWM0 */

/* - PWM0_A ------------------------------------------------------------------- */

static const unsigned int pwm0_a_pins[] = {

	/* PWM0_A */

	RCAR_GP_PIN(1, 15),

};

static const unsigned int pwm0_mux[] = {

	PWM0_MARK,

static const unsigned int pwm0_a_mux[] = {

	PWM0_A_MARK,

};



/* - PWM1 ------------------------------------------------------------------- */

static const unsigned int pwm1_pins[] = {

	/* PWM1 */

/* - PWM1_A ------------------------------------------------------------------- */

static const unsigned int pwm1_a_pins[] = {

	/* PWM1_A */

	RCAR_GP_PIN(3, 13),

};

static const unsigned int pwm1_a_mux[] = {

	PWM1_A_MARK,

};



/* - PWM1_B ------------------------------------------------------------------- */

static const unsigned int pwm1_b_pins[] = {

	/* PWM1_B */

	RCAR_GP_PIN(2, 13),

};

static const unsigned int pwm1_mux[] = {

	PWM1_MARK,

static const unsigned int pwm1_b_mux[] = {

	PWM1_B_MARK,

};



/* - PWM2 ------------------------------------------------------------------- */

static const unsigned int pwm2_pins[] = {

	/* PWM2 */

/* - PWM2_B ------------------------------------------------------------------- */

static const unsigned int pwm2_b_pins[] = {

	/* PWM2_B */

	RCAR_GP_PIN(2, 14),

};

static const unsigned int pwm2_mux[] = {

	PWM2_MARK,

static const unsigned int pwm2_b_mux[] = {

	PWM2_B_MARK,

};



/* - PWM3 ------------------------------------------------------------------- */

static const unsigned int pwm3_pins[] = {

	/* PWM3 */

/* - PWM3_A ------------------------------------------------------------------- */

static const unsigned int pwm3_a_pins[] = {

	/* PWM3_A */

	RCAR_GP_PIN(1, 22),

};

static const unsigned int pwm3_mux[] = {

	PWM3_MARK,

static const unsigned int pwm3_a_mux[] = {

	PWM3_A_MARK,

};



/* - PWM3_B ------------------------------------------------------------------- */

static const unsigned int pwm3_b_pins[] = {

	/* PWM3_B */

	RCAR_GP_PIN(2, 15),

};

static const unsigned int pwm3_b_mux[] = {

	PWM3_B_MARK,

};



/* - PWM4 ------------------------------------------------------------------- */
@@ -2102,22 +2122,22 @@ static const unsigned int pwm7_mux[] = { 
	PWM7_MARK,

};



/* - PWM8 ------------------------------------------------------------------- */

static const unsigned int pwm8_pins[] = {

	/* PWM8 */

/* - PWM8_A ------------------------------------------------------------------- */

static const unsigned int pwm8_a_pins[] = {

	/* PWM8_A */

	RCAR_GP_PIN(1, 13),

};

static const unsigned int pwm8_mux[] = {

	PWM8_MARK,

static const unsigned int pwm8_a_mux[] = {

	PWM8_A_MARK,

};



/* - PWM9 ------------------------------------------------------------------- */

static const unsigned int pwm9_pins[] = {

	/* PWM9 */

/* - PWM9_A ------------------------------------------------------------------- */

static const unsigned int pwm9_a_pins[] = {

	/* PWM9_A */

	RCAR_GP_PIN(1, 14),

};

static const unsigned int pwm9_mux[] = {

	PWM9_MARK,

static const unsigned int pwm9_a_mux[] = {

	PWM9_A_MARK,

};



/* - QSPI0 ------------------------------------------------------------------ */
@@ -2555,16 +2575,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { 
	SH_PFC_PIN_GROUP(pcie0_clkreq_n),

	SH_PFC_PIN_GROUP(pcie1_clkreq_n),



	SH_PFC_PIN_GROUP(pwm0),

	SH_PFC_PIN_GROUP(pwm1),

	SH_PFC_PIN_GROUP(pwm2),

	SH_PFC_PIN_GROUP(pwm3),

	SH_PFC_PIN_GROUP(pwm0_a),		/* suffix might be updated */

	SH_PFC_PIN_GROUP(pwm1_a),

	SH_PFC_PIN_GROUP(pwm1_b),

	SH_PFC_PIN_GROUP(pwm2_b),		/* suffix might be updated */

	SH_PFC_PIN_GROUP(pwm3_a),

	SH_PFC_PIN_GROUP(pwm3_b),

	SH_PFC_PIN_GROUP(pwm4),

	SH_PFC_PIN_GROUP(pwm5),

	SH_PFC_PIN_GROUP(pwm6),

	SH_PFC_PIN_GROUP(pwm7),

	SH_PFC_PIN_GROUP(pwm8),

	SH_PFC_PIN_GROUP(pwm9),

	SH_PFC_PIN_GROUP(pwm8_a),		/* suffix might be updated */

	SH_PFC_PIN_GROUP(pwm9_a),		/* suffix might be updated */



	SH_PFC_PIN_GROUP(qspi0_ctrl),

	BUS_DATA_PIN_GROUP(qspi0_data, 2),
@@ -2812,19 +2834,23 @@ static const char * const pcie_groups[] = { 
};



static const char * const pwm0_groups[] = {

	"pwm0",

	/* suffix might be updated */

	"pwm0_a",

};



static const char * const pwm1_groups[] = {

	"pwm1",

	"pwm1_a",

	"pwm1_b",

};



static const char * const pwm2_groups[] = {

	"pwm2",

	/* suffix might be updated */

	"pwm2_b",

};



static const char * const pwm3_groups[] = {

	"pwm3",

	"pwm3_a",

	"pwm3_b",

};



static const char * const pwm4_groups[] = {
@@ -2844,11 +2870,13 @@ static const char * const pwm7_groups[] = { 
};



static const char * const pwm8_groups[] = {

	"pwm8",

	/* suffix might be updated */

	"pwm8_a",

};



static const char * const pwm9_groups[] = {

	"pwm9",

	/* suffix might be updated */

	"pwm9_a",

};



static const char * const qspi0_groups[] = {