Commit c6e155e8 authored by James Morse's avatar James Morse Committed by Will Deacon
Browse files

arm64/sysreg: Standardise naming for MVFR2_EL1 



To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.

Ensure symbols for the MVFR2_EL1 register use lower-case for feature
names where the arm-arm does the same.

No functional change.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-16-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent d3e1aa85

arch/arm64/include/asm/sysreg.h

+2 −2
Original line number Diff line number Diff line
@@ -813,8 +813,8 @@ 
#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT		ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT

#endif



#define MVFR2_FPMISC_SHIFT		4

#define MVFR2_SIMDMISC_SHIFT		0

#define MVFR2_EL1_FPMisc_SHIFT		4

#define MVFR2_EL1_SIMDMisc_SHIFT		0



#define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */

#define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */

arch/arm64/kernel/cpufeature.c

+2 −2
Original line number Diff line number Diff line
@@ -453,8 +453,8 @@ static const struct arm64_ftr_bits ftr_mvfr1[] = { 
};



static const struct arm64_ftr_bits ftr_mvfr2[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0),

	ARM64_FTR_END,

};