Commit c7a895fc authored by Yoshihiro Kaneko's avatar Yoshihiro Kaneko Committed by Geert Uytterhoeven
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arm64: dts: renesas: r8a7795: Sort nodes 



Sort nodes.

If node address is present
   * Sort by node address, grouping all nodes with the same compat string
     and sorting the group alphabetically.
Else
   * Sort alphabetically

This should not have any run-time effect.

Signed-off-by: default avatarYoshihiro Kaneko <ykaneko0929@gmail.com>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent a44efeaa

arch/arm64/boot/dts/renesas/r8a7795.dtsi

+77 −77
Original line number Diff line number Diff line
@@ -2731,6 +2731,83 @@ imr-lx4@fe890000 { 
			resets = <&cpg 820>;

		};



		vspbc: vsp@fe920000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe920000 0 0x8000>;

			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 624>;

			power-domains = <&sysc R8A7795_PD_A3VP>;

			resets = <&cpg 624>;



			renesas,fcp = <&fcpvb1>;

		};



		vspbd: vsp@fe960000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe960000 0 0x8000>;

			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 626>;

			power-domains = <&sysc R8A7795_PD_A3VP>;

			resets = <&cpg 626>;



			renesas,fcp = <&fcpvb0>;

		};



		vspd0: vsp@fea20000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea20000 0 0x5000>;

			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 623>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 623>;



			renesas,fcp = <&fcpvd0>;

		};



		vspd1: vsp@fea28000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea28000 0 0x5000>;

			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 622>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 622>;



			renesas,fcp = <&fcpvd1>;

		};



		vspd2: vsp@fea30000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea30000 0 0x5000>;

			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 621>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 621>;



			renesas,fcp = <&fcpvd2>;

		};



		vspi0: vsp@fe9a0000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe9a0000 0 0x8000>;

			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 631>;

			power-domains = <&sysc R8A7795_PD_A3VP>;

			resets = <&cpg 631>;



			renesas,fcp = <&fcpvi0>;

		};



		vspi1: vsp@fe9b0000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe9b0000 0 0x8000>;

			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 630>;

			power-domains = <&sysc R8A7795_PD_A3VP>;

			resets = <&cpg 630>;



			renesas,fcp = <&fcpvi1>;

		};



		fdp1@fe940000 {

			compatible = "renesas,fdp1";

			reg = <0 0xfe940000 0 0x2400>;
@@ -2832,83 +2909,6 @@ fcpvd2: fcp@fea37000 { 
			iommus = <&ipmmu_vi1 10>;

		};



		vspbd: vsp@fe960000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe960000 0 0x8000>;

			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 626>;

			power-domains = <&sysc R8A7795_PD_A3VP>;

			resets = <&cpg 626>;



			renesas,fcp = <&fcpvb0>;

		};



		vspbc: vsp@fe920000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe920000 0 0x8000>;

			interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 624>;

			power-domains = <&sysc R8A7795_PD_A3VP>;

			resets = <&cpg 624>;



			renesas,fcp = <&fcpvb1>;

		};



		vspd0: vsp@fea20000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea20000 0 0x5000>;

			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 623>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 623>;



			renesas,fcp = <&fcpvd0>;

		};



		vspd1: vsp@fea28000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea28000 0 0x5000>;

			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 622>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 622>;



			renesas,fcp = <&fcpvd1>;

		};



		vspd2: vsp@fea30000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfea30000 0 0x5000>;

			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 621>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 621>;



			renesas,fcp = <&fcpvd2>;

		};



		vspi0: vsp@fe9a0000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe9a0000 0 0x8000>;

			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 631>;

			power-domains = <&sysc R8A7795_PD_A3VP>;

			resets = <&cpg 631>;



			renesas,fcp = <&fcpvi0>;

		};



		vspi1: vsp@fe9b0000 {

			compatible = "renesas,vsp2";

			reg = <0 0xfe9b0000 0 0x8000>;

			interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 630>;

			power-domains = <&sysc R8A7795_PD_A3VP>;

			resets = <&cpg 630>;



			renesas,fcp = <&fcpvi1>;

		};



		csi20: csi2@fea80000 {

			compatible = "renesas,r8a7795-csi2";

			reg = <0 0xfea80000 0 0x10000>;