Loading drivers/media/i2c/smiapp-pll.c +59 −51 Original line number Diff line number Diff line Loading @@ -87,6 +87,64 @@ static void print_pll(struct device *dev, struct smiapp_pll *pll) dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt_pix_clk_freq_hz); } static int check_all_bounds(struct device *dev, const struct smiapp_pll_limits *limits, struct smiapp_pll *pll) { int rval; rval = bounds_check(dev, pll->pll_ip_clk_freq_hz, limits->min_pll_ip_freq_hz, limits->max_pll_ip_freq_hz, "pll_ip_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->pll_multiplier, limits->min_pll_multiplier, limits->max_pll_multiplier, "pll_multiplier"); if (!rval) rval = bounds_check( dev, pll->pll_op_clk_freq_hz, limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz, "pll_op_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->op_sys_clk_div, limits->op.min_sys_clk_div, limits->op.max_sys_clk_div, "op_sys_clk_div"); if (!rval) rval = bounds_check( dev, pll->op_pix_clk_div, limits->op.min_pix_clk_div, limits->op.max_pix_clk_div, "op_pix_clk_div"); if (!rval) rval = bounds_check( dev, pll->op_sys_clk_freq_hz, limits->op.min_sys_clk_freq_hz, limits->op.max_sys_clk_freq_hz, "op_sys_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->op_pix_clk_freq_hz, limits->op.min_pix_clk_freq_hz, limits->op.max_pix_clk_freq_hz, "op_pix_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->vt_sys_clk_freq_hz, limits->vt.min_sys_clk_freq_hz, limits->vt.max_sys_clk_freq_hz, "vt_sys_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->vt_pix_clk_freq_hz, limits->vt.min_pix_clk_freq_hz, limits->vt.max_pix_clk_freq_hz, "vt_pix_clk_freq_hz"); return rval; } /* * Heuristically guess the PLL tree for a given common multiplier and * divisor. Begin with the operational timing and continue to video Loading Loading @@ -117,7 +175,6 @@ static int __smiapp_pll_calculate(struct device *dev, uint32_t min_vt_div, max_vt_div, vt_div; uint32_t min_sys_div, max_sys_div; unsigned int i; int rval; /* * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be Loading Loading @@ -323,56 +380,7 @@ static int __smiapp_pll_calculate(struct device *dev, pll->pixel_rate_csi = pll->op_pix_clk_freq_hz * lane_op_clock_ratio; rval = bounds_check(dev, pll->pll_ip_clk_freq_hz, limits->min_pll_ip_freq_hz, limits->max_pll_ip_freq_hz, "pll_ip_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->pll_multiplier, limits->min_pll_multiplier, limits->max_pll_multiplier, "pll_multiplier"); if (!rval) rval = bounds_check( dev, pll->pll_op_clk_freq_hz, limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz, "pll_op_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->op_sys_clk_div, limits->op.min_sys_clk_div, limits->op.max_sys_clk_div, "op_sys_clk_div"); if (!rval) rval = bounds_check( dev, pll->op_pix_clk_div, limits->op.min_pix_clk_div, limits->op.max_pix_clk_div, "op_pix_clk_div"); if (!rval) rval = bounds_check( dev, pll->op_sys_clk_freq_hz, limits->op.min_sys_clk_freq_hz, limits->op.max_sys_clk_freq_hz, "op_sys_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->op_pix_clk_freq_hz, limits->op.min_pix_clk_freq_hz, limits->op.max_pix_clk_freq_hz, "op_pix_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->vt_sys_clk_freq_hz, limits->vt.min_sys_clk_freq_hz, limits->vt.max_sys_clk_freq_hz, "vt_sys_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->vt_pix_clk_freq_hz, limits->vt.min_pix_clk_freq_hz, limits->vt.max_pix_clk_freq_hz, "vt_pix_clk_freq_hz"); return rval; return check_all_bounds(dev, limits, pll); } int smiapp_pll_calculate(struct device *dev, Loading Loading
drivers/media/i2c/smiapp-pll.c +59 −51 Original line number Diff line number Diff line Loading @@ -87,6 +87,64 @@ static void print_pll(struct device *dev, struct smiapp_pll *pll) dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt_pix_clk_freq_hz); } static int check_all_bounds(struct device *dev, const struct smiapp_pll_limits *limits, struct smiapp_pll *pll) { int rval; rval = bounds_check(dev, pll->pll_ip_clk_freq_hz, limits->min_pll_ip_freq_hz, limits->max_pll_ip_freq_hz, "pll_ip_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->pll_multiplier, limits->min_pll_multiplier, limits->max_pll_multiplier, "pll_multiplier"); if (!rval) rval = bounds_check( dev, pll->pll_op_clk_freq_hz, limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz, "pll_op_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->op_sys_clk_div, limits->op.min_sys_clk_div, limits->op.max_sys_clk_div, "op_sys_clk_div"); if (!rval) rval = bounds_check( dev, pll->op_pix_clk_div, limits->op.min_pix_clk_div, limits->op.max_pix_clk_div, "op_pix_clk_div"); if (!rval) rval = bounds_check( dev, pll->op_sys_clk_freq_hz, limits->op.min_sys_clk_freq_hz, limits->op.max_sys_clk_freq_hz, "op_sys_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->op_pix_clk_freq_hz, limits->op.min_pix_clk_freq_hz, limits->op.max_pix_clk_freq_hz, "op_pix_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->vt_sys_clk_freq_hz, limits->vt.min_sys_clk_freq_hz, limits->vt.max_sys_clk_freq_hz, "vt_sys_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->vt_pix_clk_freq_hz, limits->vt.min_pix_clk_freq_hz, limits->vt.max_pix_clk_freq_hz, "vt_pix_clk_freq_hz"); return rval; } /* * Heuristically guess the PLL tree for a given common multiplier and * divisor. Begin with the operational timing and continue to video Loading Loading @@ -117,7 +175,6 @@ static int __smiapp_pll_calculate(struct device *dev, uint32_t min_vt_div, max_vt_div, vt_div; uint32_t min_sys_div, max_sys_div; unsigned int i; int rval; /* * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be Loading Loading @@ -323,56 +380,7 @@ static int __smiapp_pll_calculate(struct device *dev, pll->pixel_rate_csi = pll->op_pix_clk_freq_hz * lane_op_clock_ratio; rval = bounds_check(dev, pll->pll_ip_clk_freq_hz, limits->min_pll_ip_freq_hz, limits->max_pll_ip_freq_hz, "pll_ip_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->pll_multiplier, limits->min_pll_multiplier, limits->max_pll_multiplier, "pll_multiplier"); if (!rval) rval = bounds_check( dev, pll->pll_op_clk_freq_hz, limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz, "pll_op_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->op_sys_clk_div, limits->op.min_sys_clk_div, limits->op.max_sys_clk_div, "op_sys_clk_div"); if (!rval) rval = bounds_check( dev, pll->op_pix_clk_div, limits->op.min_pix_clk_div, limits->op.max_pix_clk_div, "op_pix_clk_div"); if (!rval) rval = bounds_check( dev, pll->op_sys_clk_freq_hz, limits->op.min_sys_clk_freq_hz, limits->op.max_sys_clk_freq_hz, "op_sys_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->op_pix_clk_freq_hz, limits->op.min_pix_clk_freq_hz, limits->op.max_pix_clk_freq_hz, "op_pix_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->vt_sys_clk_freq_hz, limits->vt.min_sys_clk_freq_hz, limits->vt.max_sys_clk_freq_hz, "vt_sys_clk_freq_hz"); if (!rval) rval = bounds_check( dev, pll->vt_pix_clk_freq_hz, limits->vt.min_pix_clk_freq_hz, limits->vt.max_pix_clk_freq_hz, "vt_pix_clk_freq_hz"); return rval; return check_all_bounds(dev, limits, pll); } int smiapp_pll_calculate(struct device *dev, Loading