Commit c8ffbd43 authored by Smitha T Murthy's avatar Smitha T Murthy Committed by Mauro Carvalho Chehab
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media: s5p-mfc: Use min scratch buffer size as provided by F/W 



After MFC v8.0, mfc f/w lets the driver know how much scratch buffer
size is required for decoder. If mfc f/w has the functionality,
E_MIN_SCRATCH_BUFFER_SIZE, driver can know how much scratch buffer size
is required for encoder too.

Signed-off-by: default avatarSmitha T Murthy <smitha.t@samsung.com>
Reviewed-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Acked-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@s-opensource.com>
parent b1394dc1

drivers/media/platform/s5p-mfc/regs-mfc-v8.h

+2 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 


/* Additional registers for v8 */

#define S5P_FIMV_D_MVC_NUM_VIEWS_V8		0xf104

#define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8	0xf108

#define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8	0xf144

#define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8	0xf148

#define S5P_FIMV_D_MV_BUFFER_SIZE_V8		0xf150
@@ -84,6 +85,7 @@ 


#define S5P_FIMV_E_VBV_BUFFER_SIZE_V8		0xf78c

#define S5P_FIMV_E_VBV_INIT_DELAY_V8		0xf790

#define S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8   0xf894



#define S5P_FIMV_E_ASPECT_RATIO_V8		0xfb4c

#define S5P_FIMV_E_EXTENDED_SAR_V8		0xfb50

drivers/media/platform/s5p-mfc/s5p_mfc.c

+2 −0
Original line number Diff line number Diff line
@@ -526,6 +526,8 @@ static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx, 
				dev);

		ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,

				dev);

		ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops,

						get_min_scratch_buf_size, dev);

		if (ctx->img_width == 0 || ctx->img_height == 0)

			ctx->state = MFCINST_ERROR;

		else

drivers/media/platform/s5p-mfc/s5p_mfc_common.h

+1 −0
Original line number Diff line number Diff line
@@ -716,6 +716,7 @@ void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq); 
#define IS_MFCV7_PLUS(dev)	(dev->variant->version >= 0x70 ? 1 : 0)

#define IS_MFCV8_PLUS(dev)	(dev->variant->version >= 0x80 ? 1 : 0)

#define IS_MFCV10(dev)		(dev->variant->version >= 0xA0 ? 1 : 0)

#define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10(dev))



#define MFC_V5_BIT	BIT(0)

#define MFC_V6_BIT	BIT(1)

drivers/media/platform/s5p-mfc/s5p_mfc_enc.c

+5 −0
Original line number Diff line number Diff line
@@ -813,6 +813,11 @@ static int enc_post_seq_start(struct s5p_mfc_ctx *ctx) 
				get_enc_dpb_count, dev);

		if (ctx->pb_count < enc_pb_count)

			ctx->pb_count = enc_pb_count;

		if (FW_HAS_E_MIN_SCRATCH_BUF(dev)) {

			ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops,

					get_e_min_scratch_buf_size, dev);

			ctx->bank1.size += ctx->scratch_buf_size;

		}

		ctx->state = MFCINST_HEAD_PRODUCED;

	}

drivers/media/platform/s5p-mfc/s5p_mfc_opr.h

+4 −0
Original line number Diff line number Diff line
@@ -169,6 +169,7 @@ struct s5p_mfc_regs { 
	void __iomem *d_decoded_third_addr;/* only v7 */

	void __iomem *d_used_dpb_flag_upper;/* v7 and v8 */

	void __iomem *d_used_dpb_flag_lower;/* v7 and v8 */

	void __iomem *d_min_scratch_buffer_size; /* v10 */



	/* encoder registers */

	void __iomem *e_frame_width;
@@ -268,6 +269,7 @@ struct s5p_mfc_regs { 
	void __iomem *e_vp8_hierarchical_qp_layer0;/* v7 and v8 */

	void __iomem *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */

	void __iomem *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */

	void __iomem *e_min_scratch_buffer_size; /* v10 */

};



struct s5p_mfc_hw_ops {
@@ -311,6 +313,8 @@ struct s5p_mfc_hw_ops { 
	unsigned int (*get_pic_type_bot)(struct s5p_mfc_ctx *ctx);

	unsigned int (*get_crop_info_h)(struct s5p_mfc_ctx *ctx);

	unsigned int (*get_crop_info_v)(struct s5p_mfc_ctx *ctx);

	int (*get_min_scratch_buf_size)(struct s5p_mfc_dev *dev);

	int (*get_e_min_scratch_buf_size)(struct s5p_mfc_dev *dev);

};



void s5p_mfc_init_hw_ops(struct s5p_mfc_dev *dev);