Commit c9477f38 authored by Kukjin Kim's avatar Kukjin Kim
Browse files

Merge branch 'next-samsung-board' into next-samsung-devel-2

parents c37b2504 25201233

arch/arm/configs/exynos4_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ CONFIG_MACH_SMDKV310=y 
CONFIG_MACH_ARMLEX4210=y

CONFIG_MACH_UNIVERSAL_C210=y

CONFIG_MACH_NURI=y

CONFIG_MACH_ORIGEN=y

CONFIG_NO_HZ=y

CONFIG_HIGH_RES_TIMERS=y

CONFIG_SMP=y

arch/arm/mach-exynos4/Kconfig

+40 −0
Original line number Diff line number Diff line
@@ -15,6 +15,11 @@ config CPU_EXYNOS4210 
	help

	  Enable EXYNOS4210 CPU support



config SOC_EXYNOS4212

	bool

	help

	  Enable EXYNOS4212 SoC support



config EXYNOS4_MCT

	bool

	default y
@@ -111,6 +116,8 @@ config EXYNOS4_SETUP_USB_PHY 


menu "EXYNOS4 Machines"



comment "EXYNOS4210 Boards"



config MACH_SMDKC210

	bool "SMDKC210"

	select MACH_SMDKV310
@@ -203,6 +210,39 @@ config MACH_NURI 
	help

	  Machine support for Samsung Mobile NURI Board.



config MACH_ORIGEN

	bool "ORIGEN"

	select CPU_EXYNOS4210

	select S3C_DEV_RTC

	select S3C_DEV_WDT

	select S3C_DEV_HSMMC2

	select EXYNOS4_SETUP_SDHCI

	help

	  Machine support for ORIGEN based on Samsung EXYNOS4210



comment "EXYNOS4212 Boards"



config MACH_SMDK4212

	bool "SMDK4212"

	select SOC_EXYNOS4212

	select S3C_DEV_HSMMC2

	select S3C_DEV_HSMMC3

	select S3C_DEV_I2C1

	select S3C_DEV_I2C3

	select S3C_DEV_I2C7

	select S3C_DEV_RTC

	select S3C_DEV_WDT

	select SAMSUNG_DEV_BACKLIGHT

	select SAMSUNG_DEV_KEYPAD

	select SAMSUNG_DEV_PWM

	select EXYNOS4_SETUP_I2C1

	select EXYNOS4_SETUP_I2C3

	select EXYNOS4_SETUP_I2C7

	select EXYNOS4_SETUP_KEYPAD

	select EXYNOS4_SETUP_SDHCI

	help

	  Machine support for Samsung SMDK4212



endmenu



comment "Configuration for HSMMC bus width"

arch/arm/mach-exynos4/Makefile

+7 −2
Original line number Diff line number Diff line
@@ -12,8 +12,10 @@ obj- := 


# Core support for EXYNOS4 system



obj-$(CONFIG_CPU_EXYNOS4210)	+= cpu.o init.o clock.o irq-combiner.o

obj-$(CONFIG_CPU_EXYNOS4210)	+= setup-i2c0.o irq-eint.o dma.o pmu.o

obj-$(CONFIG_ARCH_EXYNOS4)	+= cpu.o init.o clock.o irq-combiner.o

obj-$(CONFIG_ARCH_EXYNOS4)	+= setup-i2c0.o irq-eint.o dma.o pmu.o

obj-$(CONFIG_CPU_EXYNOS4210)	+= clock-exynos4210.o

obj-$(CONFIG_SOC_EXYNOS4212)	+= clock-exynos4212.o

obj-$(CONFIG_PM)		+= pm.o sleep.o

obj-$(CONFIG_CPU_IDLE)		+= cpuidle.o
@@ -30,6 +32,9 @@ obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o 
obj-$(CONFIG_MACH_ARMLEX4210)		+= mach-armlex4210.o

obj-$(CONFIG_MACH_UNIVERSAL_C210)	+= mach-universal_c210.o

obj-$(CONFIG_MACH_NURI)			+= mach-nuri.o

obj-$(CONFIG_MACH_ORIGEN)		+= mach-origen.o



obj-$(CONFIG_MACH_SMDK4212)		+= mach-smdk4212.o



# device support

arch/arm/mach-exynos4/clock-exynos4210.c

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/*

 * linux/arch/arm/mach-exynos4/clock-exynos4210.c

 *

 * Copyright (c) 2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * EXYNOS4210 - Clock support

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/



#include <linux/kernel.h>

#include <linux/err.h>

#include <linux/clk.h>

#include <linux/io.h>

#include <linux/syscore_ops.h>



#include <plat/cpu-freq.h>

#include <plat/clock.h>

#include <plat/cpu.h>

#include <plat/pll.h>

#include <plat/s5p-clock.h>

#include <plat/clock-clksrc.h>

#include <plat/exynos4.h>

#include <plat/pm.h>



#include <mach/hardware.h>

#include <mach/map.h>

#include <mach/regs-clock.h>

#include <mach/exynos4-clock.h>



static struct sleep_save exynos4210_clock_save[] = {

	SAVE_ITEM(S5P_CLKSRC_IMAGE),

	SAVE_ITEM(S5P_CLKSRC_LCD1),

	SAVE_ITEM(S5P_CLKDIV_IMAGE),

	SAVE_ITEM(S5P_CLKDIV_LCD1),

	SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),

	SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210),

	SAVE_ITEM(S5P_CLKGATE_IP_LCD1),

	SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210),

};



static struct clksrc_clk *sysclks[] = {

	/* nothing here yet */

};



static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)

{

	return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);

}



static struct clksrc_clk clksrcs[] = {

	{

		.clk		= {

			.name		= "sclk_sata",

			.id		= -1,

			.enable		= exynos4_clksrc_mask_fsys_ctrl,

			.ctrlbit	= (1 << 24),

		},

		.sources = &clkset_mout_corebus,

		.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },

		.reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },

	}, {

		.clk		= {

			.name		= "sclk_fimd",

			.devname	= "exynos4-fb.1",

			.enable		= exynos4_clksrc_mask_lcd1_ctrl,

			.ctrlbit	= (1 << 0),

		},

		.sources = &clkset_group,

		.reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },

		.reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },

	},

};



static struct clk init_clocks_off[] = {

	{

		.name		= "sataphy",

		.id		= -1,

		.parent		= &clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 3),

	}, {

		.name		= "sata",

		.id		= -1,

		.parent		= &clk_aclk_133.clk,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 10),

	}, {

		.name		= "fimd",

		.devname	= "exynos4-fb.1",

		.enable		= exynos4_clk_ip_lcd1_ctrl,

		.ctrlbit	= (1 << 0),

	},

};



#ifdef CONFIG_PM_SLEEP

static int exynos4210_clock_suspend(void)

{

	s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));



	return 0;

}



static void exynos4210_clock_resume(void)

{

	s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));

}



#else

#define exynos4210_clock_suspend NULL

#define exynos4210_clock_resume NULL

#endif



struct syscore_ops exynos4210_clock_syscore_ops = {

	.suspend	= exynos4210_clock_suspend,

	.resume		= exynos4210_clock_resume,

};



void __init exynos4210_register_clocks(void)

{

	int ptr;



	clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU;

	clk_mout_mpll.reg_src.shift = 8;

	clk_mout_mpll.reg_src.size = 1;



	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)

		s3c_register_clksrc(sysclks[ptr], 1);



	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));



	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));



	register_syscore_ops(&exynos4210_clock_syscore_ops);

}

arch/arm/mach-exynos4/clock-exynos4212.c

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/*

 * linux/arch/arm/mach-exynos4/clock-exynos4212.c

 *

 * Copyright (c) 2011 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com

 *

 * EXYNOS4212 - Clock support

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/



#include <linux/kernel.h>

#include <linux/err.h>

#include <linux/clk.h>

#include <linux/io.h>

#include <linux/syscore_ops.h>



#include <plat/cpu-freq.h>

#include <plat/clock.h>

#include <plat/cpu.h>

#include <plat/pll.h>

#include <plat/s5p-clock.h>

#include <plat/clock-clksrc.h>

#include <plat/exynos4.h>

#include <plat/pm.h>



#include <mach/hardware.h>

#include <mach/map.h>

#include <mach/regs-clock.h>

#include <mach/exynos4-clock.h>



static struct sleep_save exynos4212_clock_save[] = {

	SAVE_ITEM(S5P_CLKSRC_IMAGE),

	SAVE_ITEM(S5P_CLKDIV_IMAGE),

	SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212),

	SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212),

};



static struct clk *clk_src_mpll_user_list[] = {

	[0] = &clk_fin_mpll,

	[1] = &clk_mout_mpll.clk,

};



static struct clksrc_sources clk_src_mpll_user = {

	.sources	= clk_src_mpll_user_list,

	.nr_sources	= ARRAY_SIZE(clk_src_mpll_user_list),

};



static struct clksrc_clk clk_mout_mpll_user = {

	.clk = {

		.name		= "mout_mpll_user",

	},

	.sources	= &clk_src_mpll_user,

	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 },

};



static struct clksrc_clk *sysclks[] = {

	&clk_mout_mpll_user,

};



static struct clksrc_clk clksrcs[] = {

	/* nothing here yet */

};



static struct clk init_clocks_off[] = {

	/* nothing here yet */

};



#ifdef CONFIG_PM_SLEEP

static int exynos4212_clock_suspend(void)

{

	s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));



	return 0;

}



static void exynos4212_clock_resume(void)

{

	s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));

}



#else

#define exynos4212_clock_suspend NULL

#define exynos4212_clock_resume NULL

#endif



struct syscore_ops exynos4212_clock_syscore_ops = {

	.suspend	= exynos4212_clock_suspend,

	.resume		= exynos4212_clock_resume,

};



void __init exynos4212_register_clocks(void)

{

	int ptr;



	/* usbphy1 is removed */

	clkset_group_list[4] = NULL;



	/* mout_mpll_user is used */

	clkset_group_list[6] = &clk_mout_mpll_user.clk;

	clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;



	clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC;

	clk_mout_mpll.reg_src.shift = 12;

	clk_mout_mpll.reg_src.size = 1;



	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)

		s3c_register_clksrc(sysclks[ptr], 1);



	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));



	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));



	register_syscore_ops(&exynos4212_clock_syscore_ops);

}