Commit c94ea32c authored by Pali Rohár's avatar Pali Rohár Committed by Lorenzo Pieralisi
Browse files

PCI: mvebu: Update comment for PCI_EXP_LNKCTL register on emulated bridge 

Logic and code for clearing PCI_EXP_LNKCTL_CLKREQ_EN bit is correct, but
comment describing it is misleading. PCI_EXP_LNKCTL_CLKREQ_EN bit should be
hardwired to zero but mvebu hw allows to change it.

Link: https://lore.kernel.org/r/20220104153529.31647-11-pali@kernel.org


Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
parent d76a6ed0

drivers/pci/controller/pci-mvebu.c

+3 −4
Original line number Diff line number Diff line
@@ -663,10 +663,9 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, 


	case PCI_EXP_LNKCTL:

		/*

		 * If we don't support CLKREQ, we must ensure that the

		 * CLKREQ enable bit always reads zero.  Since we haven't

		 * had this capability, and it's dependent on board wiring,

		 * disable it for the time being.

		 * PCIe requires that the Enable Clock Power Management bit

		 * is hard-wired to zero for downstream ports but HW allows

		 * to change it.

		 */

		new &= ~PCI_EXP_LNKCTL_CLKREQ_EN;