Commit c9c4ddb2 authored by Petlozu Pravareshwar's avatar Petlozu Pravareshwar Committed by Thierry Reding
Browse files

soc/tegra: pmc: Add I/O pad table for Tegra234 



Add I/O pad table for Tegra234 to allow configuring DPD mode and
switching the pins to 1.8V or 3.3V as needed.

On Tegra234, DPD registers are reorganized such that there is a DPD_REQ
register and a DPD_STATUS register per pad group. Update the PMC driver
accordingly.

While at it, use the generated tables from tegra-pinmux-scripts to make
the formatting of these tables more consistent.

Signed-off-by: default avatarPetlozu Pravareshwar <petlozup@nvidia.com>
[treding@nvidia.com: generate tables from tegra-pinmux-scripts]
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent cc5b2ad5

drivers/soc/tegra/pmc.c

+403 −253

File changed.

Preview size limit exceeded, changes collapsed.

include/soc/tegra/pmc.h

+3 −3
Original line number Diff line number Diff line
@@ -118,9 +118,9 @@ enum tegra_io_pad { 
	TEGRA_IO_PAD_PEX_CLK_2,

	TEGRA_IO_PAD_PEX_CNTRL,

	TEGRA_IO_PAD_PEX_CTL2,

	TEGRA_IO_PAD_PEX_L0_RST_N,

	TEGRA_IO_PAD_PEX_L1_RST_N,

	TEGRA_IO_PAD_PEX_L5_RST_N,

	TEGRA_IO_PAD_PEX_L0_RST,

	TEGRA_IO_PAD_PEX_L1_RST,

	TEGRA_IO_PAD_PEX_L5_RST,

	TEGRA_IO_PAD_PWR_CTL,

	TEGRA_IO_PAD_SDMMC1,

	TEGRA_IO_PAD_SDMMC1_HV,