Commit c9f30e3d authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Bjorn Andersson
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ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane} 



There is only one PCIe PHY in this SoC, so there is no need to add an
index to the suffix. This also matches the naming convention of the PCIe
controller.

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230308082424.140224-7-manivannan.sadhasivam@linaro.org
parent 3b76b736

arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts

+1 −1
Original line number Diff line number Diff line
@@ -242,7 +242,7 @@ &ipa { 
	status = "okay";

};



&pcie0_phy {

&pcie_phy {

	status = "okay";



	vdda-phy-supply = <&vreg_l1e_bb_1p2>;

arch/arm/boot/dts/qcom-sdx55.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -335,7 +335,7 @@ pcie_ep: pcie-ep@1c00000 { 
			resets = <&gcc GCC_PCIE_BCR>;

			reset-names = "core";

			power-domains = <&gcc PCIE_GDSC>;

			phys = <&pcie0_lane>;

			phys = <&pcie_lane>;

			phy-names = "pciephy";

			max-link-speed = <3>;

			num-lanes = <2>;
@@ -343,7 +343,7 @@ pcie_ep: pcie-ep@1c00000 { 
			status = "disabled";

		};



		pcie0_phy: phy@1c07000 {

		pcie_phy: phy@1c07000 {

			compatible = "qcom,sdx55-qmp-pcie-phy";

			reg = <0x01c07000 0x1c4>;

			#address-cells = <1>;
@@ -363,7 +363,7 @@ pcie0_phy: phy@1c07000 { 


			status = "disabled";



			pcie0_lane: lanes@1c06000 {

			pcie_lane: lanes@1c06000 {

				reg = <0x01c06000 0x104>, /* tx0 */

				      <0x01c06200 0x328>, /* rx0 */

				      <0x01c07200 0x1e8>, /* pcs */