Commit ca4ba339 authored by Horace Chen's avatar Horace Chen Committed by Alex Deucher
Browse files

drm/amdgpu: add a compute pipe reset for RS64 



[Why]
Under SR-IOV, we are not sure whether pipe status is
good or not when doing initialization. The compute engine
maybe fail to bringup if pipe status is bad.

[How]
Do an RS64 pipe reset for MEC before we do initialization.
Also apply to bare-metal.

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarHorace Chen <horace.chen@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 119dc6c5

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+15 −0
Original line number Diff line number Diff line
@@ -2725,6 +2725,21 @@ static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev) 
					mec_hdr->ucode_start_addr_hi >> 2);

	}

	soc21_grbm_select(adev, 0, 0, 0, 0);



	/* reset mec pipe */

	tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);

	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);

	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);

	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);

	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);

	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);



	/* clear mec pipe reset */

	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);

	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);

	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);

	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);

	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);

}



static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)