Commit cad3fab4 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Extract skl_crtc_calc_dbuf_bw() 



Extract the dbuf slice data_rate calculation into a small
helper. Should make it a bit easier to handle the different
color planes of planar formats correctly.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220118092354.11631-7-ville.syrjala@linux.intel.com


Reviewed-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
parent 04d4e167

drivers/gpu/drm/i915/display/intel_bw.c

+44 −38
Original line number Diff line number Diff line
@@ -673,49 +673,34 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state) 
	return to_intel_bw_state(bw_state);

}



int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)

static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,

				  const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(state->base.dev);

	struct intel_bw_state *new_bw_state = NULL;

	struct intel_bw_state *old_bw_state = NULL;

	const struct intel_crtc_state *crtc_state;

	struct intel_crtc *crtc;

	int max_bw = 0;

	enum pipe pipe;

	int i;



	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];

	enum plane_id plane_id;

		struct intel_dbuf_bw *crtc_bw;



		new_bw_state = intel_atomic_get_bw_state(state);

		if (IS_ERR(new_bw_state))

			return PTR_ERR(new_bw_state);



		old_bw_state = intel_atomic_get_old_bw_state(state);



		crtc_bw = &new_bw_state->dbuf_bw[crtc->pipe];



	memset(&crtc_bw->used_bw, 0, sizeof(crtc_bw->used_bw));



	if (!crtc_state->hw.active)

			continue;

		return;



	for_each_plane_id_on_crtc(crtc, plane_id) {

			const struct skl_ddb_entry *plane_alloc =

		const struct skl_ddb_entry *ddb_y =

			&crtc_state->wm.skl.plane_ddb_y[plane_id];

			const struct skl_ddb_entry *uv_plane_alloc =

		const struct skl_ddb_entry *ddb_uv =

			&crtc_state->wm.skl.plane_ddb_uv[plane_id];

		unsigned int data_rate = crtc_state->data_rate[plane_id];

		unsigned int dbuf_mask = 0;

		enum dbuf_slice slice;



			dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc);

			dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc);

		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_y);

		dbuf_mask |= skl_ddb_dbuf_slice_mask(i915, ddb_uv);



		/*

		 * FIXME: To calculate that more properly we probably

			 * need to to split per plane data_rate into data_rate_y

		 * need to split per plane data_rate into data_rate_y

		 * and data_rate_uv for multiplanar formats in order not

		 * to get accounted those twice if they happen to reside

		 * on different slices.
@@ -726,11 +711,32 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) 
		 * pessimistic, which shouldn't pose any significant

		 * problem anyway.

		 */

			for_each_dbuf_slice_in_mask(dev_priv, slice, dbuf_mask)

		for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask)

			crtc_bw->used_bw[slice] += data_rate;

	}

}



int skl_bw_calc_min_cdclk(struct intel_atomic_state *state)

{

	struct drm_i915_private *dev_priv = to_i915(state->base.dev);

	struct intel_bw_state *new_bw_state = NULL;

	struct intel_bw_state *old_bw_state = NULL;

	const struct intel_crtc_state *crtc_state;

	struct intel_crtc *crtc;

	int max_bw = 0;

	enum pipe pipe;

	int i;



	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {

		new_bw_state = intel_atomic_get_bw_state(state);

		if (IS_ERR(new_bw_state))

			return PTR_ERR(new_bw_state);



		old_bw_state = intel_atomic_get_old_bw_state(state);



		skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);

	}



	if (!old_bw_state)

		return 0;