Commit cb4b2d26 authored by Alexandre Torgue's avatar Alexandre Torgue
Browse files

ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15 



Using GIC_CPU_MASK_SIMPLE(x), x should reflect the number of CPUs.
STM32MP151 is a single A7.
STM32MP153/157 is a dual A7.

Signed-off-by: default avatarAlexandre Torgue <alexandre.torgue@foss.st.com>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
parent bf5f07e7

arch/arm/boot/dts/stm32mp151.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -45,10 +45,10 @@ intc: interrupt-controller@a0021000 { 


	timer {

		compatible = "arm,armv7-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;

		interrupt-parent = <&intc>;

	};

arch/arm/boot/dts/stm32mp153.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -22,6 +22,13 @@ arm-pmu { 
		interrupt-affinity = <&cpu0>, <&cpu1>;

	};



	timer {

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;

	};



	soc {

		m_can1: can@4400e000 {

			compatible = "bosch,m_can";