Commit cba9e7db authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

ARM: dts: arm: align UART node name with bindings

parent 60e6cca8
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+2 −2
Original line number Diff line number Diff line
@@ -88,12 +88,12 @@ rtc@15000000 {
			interrupts = <8>;
		};

		uart@16000000 {
		serial@16000000 {
			reg = <0x16000000 0x1000>;
			interrupts = <1>;
		};

		uart@17000000 {
		serial@17000000 {
			reg = <0x17000000 0x1000>;
			interrupts = <2>;
		};
+2 −2
Original line number Diff line number Diff line
@@ -162,7 +162,7 @@ vga_con_in: endpoint {
		};
	};

	uart@100000 {
	serial@100000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x00100000 0x1000>;
		interrupts-extended = <&impd1_vic 1>;
@@ -170,7 +170,7 @@ uart@100000 {
		clock-names = "uartclk", "apb_pclk";
	};

	uart@200000 {
	serial@200000 {
		compatible = "arm,pl011", "arm,primecell";
		reg = <0x00200000 0x1000>;
		interrupts-extended = <&impd1_vic 2>;
+2 −2
Original line number Diff line number Diff line
@@ -218,14 +218,14 @@ rtc: rtc@15000000 {
			clock-names = "apb_pclk";
		};

		uart0: uart@16000000 {
		uart0: serial@16000000 {
			compatible = "arm,pl010", "arm,primecell";
			arm,primecell-periphid = <0x00041010>;
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart1: uart@17000000 {
		uart1: serial@17000000 {
			compatible = "arm,pl010", "arm,primecell";
			arm,primecell-periphid = <0x00041010>;
			clocks = <&uartclk>, <&pclk>;
+2 −2
Original line number Diff line number Diff line
@@ -244,13 +244,13 @@ rtc@15000000 {
			clock-names = "apb_pclk";
		};

		uart@16000000 {
		serial@16000000 {
			compatible = "arm,pl011", "arm,primecell";
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart@17000000 {
		serial@17000000 {
			compatible = "arm,pl011", "arm,primecell";
			clocks = <&uartclk>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
+3 −3
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ dma@10130000 {
			clock-names = "apb_pclk";
		};

		uart0: uart@101f1000 {
		uart0: serial@101f1000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f1000 0x1000>;
			interrupts = <12>;
@@ -245,7 +245,7 @@ uart0: uart@101f1000 {
			clock-names = "uartclk", "apb_pclk";
		};

		uart1: uart@101f2000 {
		uart1: serial@101f2000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f2000 0x1000>;
			interrupts = <13>;
@@ -253,7 +253,7 @@ uart1: uart@101f2000 {
			clock-names = "uartclk", "apb_pclk";
		};

		uart2: uart@101f3000 {
		uart2: serial@101f3000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f3000 0x1000>;
			interrupts = <14>;
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