Commit cbb2f09a authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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arm64: dts: renesas: r8a774e1: Add PCIe device nodes 



Add PCIe{0,1} device nodes for R8A774E1 SoC.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarMarian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Link: https://lore.kernel.org/r/1594919915-5225-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 9123e3a7

arch/arm64/boot/dts/renesas/r8a774e1.dtsi

+46 −1
Original line number Diff line number Diff line
@@ -1517,12 +1517,57 @@ gic: interrupt-controller@f1010000 { 
		};



		pciec0: pcie@fe000000 {

			compatible = "renesas,pcie-r8a774e1",

				     "renesas,pcie-rcar-gen3";

			reg = <0 0xfe000000 0 0x80000>;

			#address-cells = <3>;

			#size-cells = <2>;

			bus-range = <0x00 0xff>;

			device_type = "pci";

			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,

				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,

				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,

				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;

			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 319>;

			status = "disabled";

		};



			/* placeholder */

		pciec1: pcie@ee800000 {

			compatible = "renesas,pcie-r8a774e1",

				     "renesas,pcie-rcar-gen3";

			reg = <0 0xee800000 0 0x80000>;

			#address-cells = <3>;

			#size-cells = <2>;

			bus-range = <0x00 0xff>;

			device_type = "pci";

			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,

				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,

				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,

				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;

			/* Map all possible DDR as inbound ranges */

			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;

			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;

			clock-names = "pcie", "pcie_bus";

			power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;

			resets = <&cpg 318>;

			status = "disabled";

		};



		hdmi0: hdmi@fead0000 {