Loading drivers/mfd/intel-lpss.c +5 −5 Original line number Diff line number Diff line Loading @@ -47,10 +47,10 @@ #define LPSS_PRIV_IDLELTR 0x14 #define LPSS_PRIV_LTR_REQ BIT(15) #define LPSS_PRIV_LTR_SCALE_MASK 0xc00 #define LPSS_PRIV_LTR_SCALE_1US 0x800 #define LPSS_PRIV_LTR_SCALE_32US 0xc00 #define LPSS_PRIV_LTR_VALUE_MASK 0x3ff #define LPSS_PRIV_LTR_SCALE_MASK GENMASK(11, 10) #define LPSS_PRIV_LTR_SCALE_1US (2 << 10) #define LPSS_PRIV_LTR_SCALE_32US (3 << 10) #define LPSS_PRIV_LTR_VALUE_MASK GENMASK(9, 0) #define LPSS_PRIV_SSP_REG 0x20 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0) Loading @@ -59,8 +59,8 @@ #define LPSS_PRIV_CAPS 0xfc #define LPSS_PRIV_CAPS_NO_IDMA BIT(8) #define LPSS_PRIV_CAPS_TYPE_MASK GENMASK(7, 4) #define LPSS_PRIV_CAPS_TYPE_SHIFT 4 #define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT) /* This matches the type field in CAPS register */ enum intel_lpss_dev_type { Loading Loading
drivers/mfd/intel-lpss.c +5 −5 Original line number Diff line number Diff line Loading @@ -47,10 +47,10 @@ #define LPSS_PRIV_IDLELTR 0x14 #define LPSS_PRIV_LTR_REQ BIT(15) #define LPSS_PRIV_LTR_SCALE_MASK 0xc00 #define LPSS_PRIV_LTR_SCALE_1US 0x800 #define LPSS_PRIV_LTR_SCALE_32US 0xc00 #define LPSS_PRIV_LTR_VALUE_MASK 0x3ff #define LPSS_PRIV_LTR_SCALE_MASK GENMASK(11, 10) #define LPSS_PRIV_LTR_SCALE_1US (2 << 10) #define LPSS_PRIV_LTR_SCALE_32US (3 << 10) #define LPSS_PRIV_LTR_VALUE_MASK GENMASK(9, 0) #define LPSS_PRIV_SSP_REG 0x20 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0) Loading @@ -59,8 +59,8 @@ #define LPSS_PRIV_CAPS 0xfc #define LPSS_PRIV_CAPS_NO_IDMA BIT(8) #define LPSS_PRIV_CAPS_TYPE_MASK GENMASK(7, 4) #define LPSS_PRIV_CAPS_TYPE_SHIFT 4 #define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT) /* This matches the type field in CAPS register */ enum intel_lpss_dev_type { Loading