Commit cd487b6d authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
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drm/amd/display: Use DPP inst instead of pipe idx for DPP DTO programming 



[Description]
- For pipe harvesting cases we must use DPP inst instead of
  pipe index for DPP related programming

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 932698c8

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+36 −2
Original line number Diff line number Diff line
@@ -255,6 +255,40 @@ static void dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, s 
	}

}



void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

		struct dc_state *context, bool safe_to_lower)

{

	int i;



	clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;

	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {

		int dpp_inst, dppclk_khz, prev_dppclk_khz;



		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;



		if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

			dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

		else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

			/* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.

			 * In this case just continue in loop

			 */

			continue;

		} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

			/* The software state is not valid if dpp resource is NULL and

			 * dppclk_khz > 0.

			 */

			ASSERT(false);

			continue;

		}



		prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];



		if (safe_to_lower || prev_dppclk_khz < dppclk_khz)

			clk_mgr->dccg->funcs->update_dpp_dto(

							clk_mgr->dccg, dpp_inst, dppclk_khz);

	}

}



static void dcn32_update_clocks_update_dentist(

		struct clk_mgr_internal *clk_mgr,

		struct dc_state *context)
@@ -524,7 +558,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, 
	if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {

		if (dpp_clock_lowered) {

			/* if clock is being lowered, increase DTO before lowering refclk */

			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

			dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

			dcn32_update_clocks_update_dentist(clk_mgr, context);

			if (clk_mgr->smu_present)

				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
@@ -536,7 +570,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, 
			 * that we do not lower dto when it is not safe to lower. We do not need to

			 * compare the current and new dppclk before calling this function.

			 */

			dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

			dcn32_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);

		}

	}

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.h

+3 −0
Original line number Diff line number Diff line
@@ -32,6 +32,9 @@ void dcn32_clk_mgr_construct(struct dc_context *ctx, 
		struct pp_smu_funcs *pp_smu,

		struct dccg *dccg);



void dcn32_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,

		struct dc_state *context, bool safe_to_lower);



void dcn32_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr);