Commit cdbb816b authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: remove check for CE in RAS error address query 



Only RAS UE error address is queried currently, no need to check CE status.

Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent faf4d8e0

drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

+3 −7
Original line number Diff line number Diff line
@@ -327,10 +327,9 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, 
		return;

	}



	/* calculate error address if ue/ce error is detected */

	/* calculate error address if ue error is detected */

	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&

	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {



		err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);

		/* the lowest lsb bits should be ignored */
@@ -343,9 +342,6 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, 
				ADDR_OF_256B_BLOCK(channel_index) |

				OFFSET_IN_256B_BLOCK(err_addr);



		/* we only save ue error information currently, ce is skipped */

		if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)

				== 1)

		amdgpu_umc_fill_error_record(err_data, err_addr,

					retired_page, channel_index, umc_inst);

	}

drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

+28 −39
Original line number Diff line number Diff line
@@ -209,10 +209,9 @@ static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev, 
	if (!err_data->err_addr)

		return;



	/* calculate error address if ue/ce error is detected */

	/* calculate error address if ue error is detected */

	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&

	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {



		err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;

		err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
@@ -228,9 +227,6 @@ static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev, 
		/* clear [C4 C3 C2] in soc physical address */

		soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT);



		/* we only save ue error information currently, ce is skipped */

		if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)

				== 1) {

		/* loop for all possibilities of [C4 C3 C2] */

		for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) {

			retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT);
@@ -246,7 +242,6 @@ static void umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev, 
		}

	}

}

}



static void umc_v6_7_ecc_info_query_ras_error_address(struct amdgpu_device *adev,

					     void *ras_error_status)
@@ -481,10 +476,9 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, 
	channel_index =

		adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];



	/* calculate error address if ue/ce error is detected */

	/* calculate error address if ue error is detected */

	if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&

	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) ||

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) ||

	    mca_addr != UMC_INVALID_ADDR) {

		if (mca_addr == UMC_INVALID_ADDR) {

			err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
@@ -505,10 +499,6 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, 
		/* clear [C4 C3 C2] in soc physical address */

		soc_pa &= ~(0x7ULL << UMC_V6_7_PA_C2_BIT);



		/* we only save ue error information currently, ce is skipped */

		if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)

				== 1 ||

		    mca_addr != UMC_INVALID_ADDR) {

		/* loop for all possibilities of [C4 C3 C2] */

		for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) {

			retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT);
@@ -523,7 +513,6 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, 
				retired_page, channel_index, umc_inst);

		}

	}

	}



	/* clear umc status */

	if (mca_addr == UMC_INVALID_ADDR)

drivers/gpu/drm/amd/amdgpu/umc_v8_10.c

+22 −30
Original line number Diff line number Diff line
@@ -208,7 +208,10 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev, 
{

	uint64_t mc_umc_status_addr;

	uint64_t mc_umc_status, err_addr;

	uint32_t channel_index;

	uint64_t mc_umc_addrt0, na_err_addr_base;

	uint64_t na_err_addr, retired_page_addr;

	uint32_t channel_index, addr_lsb, col = 0;

	int ret = 0;



	mc_umc_status_addr =

		SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);
@@ -229,13 +232,10 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev, 
					umc_inst * adev->umc.channel_inst_num +

					ch_inst];



	/* calculate error address if ue/ce error is detected */

	/* calculate error address if ue error is detected */

	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrV) == 1 &&

	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||

	     REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {

		uint32_t addr_lsb;

		uint64_t mc_umc_addrt0;

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {



		mc_umc_addrt0 = SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0);

		err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);
@@ -243,15 +243,8 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev, 


		/* the lowest lsb bits should be ignored */

		addr_lsb = REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, AddrLsb);



		err_addr &= ~((0x1ULL << addr_lsb) - 1);



		/* we only save ue error information currently, ce is skipped */

		if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {

			uint64_t na_err_addr_base = err_addr & ~(0x3ULL << UMC_V8_10_NA_C5_BIT);

			uint64_t na_err_addr, retired_page_addr;

			uint32_t col = 0;

			int ret = 0;

		na_err_addr_base = err_addr & ~(0x3ULL << UMC_V8_10_NA_C5_BIT);



		/* loop for all possibilities of [C6 C5] in normal address. */

		for (col = 0; col < UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; col++) {
@@ -270,7 +263,6 @@ static void umc_v8_10_query_error_address(struct amdgpu_device *adev, 
					retired_page_addr, channel_index, umc_inst);

		}

	}

	}



	/* clear umc status */

	WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);

drivers/gpu/drm/amd/amdgpu/umc_v8_7.c

+6 −14
Original line number Diff line number Diff line
@@ -130,10 +130,9 @@ static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev, 
	if (!err_data->err_addr)

		return;



	/* calculate error address if ue/ce error is detected */

	/* calculate error address if ue error is detected */

	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&

	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {



		err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr;

		err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
@@ -143,9 +142,6 @@ static void umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev, 
				ADDR_OF_256B_BLOCK(channel_index) |

				OFFSET_IN_256B_BLOCK(err_addr);



		/* we only save ue error information currently, ce is skipped */

		if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)

				== 1)

		amdgpu_umc_fill_error_record(err_data, err_addr,

					retired_page, channel_index, umc_inst);

	}
@@ -343,10 +339,9 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev, 
		return;

	}



	/* calculate error address if ue/ce error is detected */

	/* calculate error address if ue error is detected */

	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&

	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) {

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1) {



		err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4);

		/* the lowest lsb bits should be ignored */
@@ -359,9 +354,6 @@ static void umc_v8_7_query_error_address(struct amdgpu_device *adev, 
				ADDR_OF_256B_BLOCK(channel_index) |

				OFFSET_IN_256B_BLOCK(err_addr);



		/* we only save ue error information currently, ce is skipped */

		if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC)

				== 1)

		amdgpu_umc_fill_error_record(err_data, err_addr,

					retired_page, channel_index, umc_inst);

	}