Commit cecbb5da authored by Dan Williams's avatar Dan Williams
Browse files

cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM 



In preparation for device-memory region creation, arrange for decoders
of CXL_DEVTYPE_DEVMEM memdevs to default to CXL_DECODER_DEVMEM for their
target type.

Revisit this if a device ever shows up that wants to offer mixed HDM-H
(Host-Only Memory) and HDM-DB support, or an CXL_DEVTYPE_DEVMEM device
that supports HDM-H.

Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarDave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/168679261945.3436160.11673393474107374595.stgit@dwillia2-xfh.jf.intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 5aa39a91

drivers/cxl/core/hdm.c

+26 −9
Original line number Original line Diff line number Diff line
@@ -572,7 +572,7 @@ static void cxld_set_type(struct cxl_decoder *cxld, u32 *ctrl) 
{

{

	u32p_replace_bits(ctrl,

	u32p_replace_bits(ctrl,

			  !!(cxld->target_type == CXL_DECODER_HOSTONLYMEM),

			  !!(cxld->target_type == CXL_DECODER_HOSTONLYMEM),

			  CXL_HDM_DECODER0_CTRL_TYPE);

			  CXL_HDM_DECODER0_CTRL_HOSTONLY);

}

}





static int cxlsd_set_targets(struct cxl_switch_decoder *cxlsd, u64 *tgt)

static int cxlsd_set_targets(struct cxl_switch_decoder *cxlsd, u64 *tgt)
@@ -794,8 +794,8 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, 
			    int *target_map, void __iomem *hdm, int which,

			    int *target_map, void __iomem *hdm, int which,

			    u64 *dpa_base, struct cxl_endpoint_dvsec_info *info)

			    u64 *dpa_base, struct cxl_endpoint_dvsec_info *info)

{

{

	struct cxl_endpoint_decoder *cxled = NULL;

	u64 size, base, skip, dpa_size, lo, hi;

	u64 size, base, skip, dpa_size, lo, hi;

	struct cxl_endpoint_decoder *cxled;

	bool committed;

	bool committed;

	u32 remainder;

	u32 remainder;

	int i, rc;

	int i, rc;
@@ -828,6 +828,8 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, 
		return -ENXIO;

		return -ENXIO;

	}

	}





	if (info)

		cxled = to_cxl_endpoint_decoder(&cxld->dev);

	cxld->hpa_range = (struct range) {

	cxld->hpa_range = (struct range) {

		.start = base,

		.start = base,

		.end = base + size - 1,

		.end = base + size - 1,
@@ -838,7 +840,7 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, 
		cxld->flags |= CXL_DECODER_F_ENABLE;

		cxld->flags |= CXL_DECODER_F_ENABLE;

		if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK)

		if (ctrl & CXL_HDM_DECODER0_CTRL_LOCK)

			cxld->flags |= CXL_DECODER_F_LOCK;

			cxld->flags |= CXL_DECODER_F_LOCK;

		if (FIELD_GET(CXL_HDM_DECODER0_CTRL_TYPE, ctrl))

		if (FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl))

			cxld->target_type = CXL_DECODER_HOSTONLYMEM;

			cxld->target_type = CXL_DECODER_HOSTONLYMEM;

		else

		else

			cxld->target_type = CXL_DECODER_DEVMEM;

			cxld->target_type = CXL_DECODER_DEVMEM;
@@ -857,12 +859,28 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, 
		}

		}

		port->commit_end = cxld->id;

		port->commit_end = cxld->id;

	} else {

	} else {

		/* unless / until type-2 drivers arrive, assume type-3 */

		if (cxled) {

		if (FIELD_GET(CXL_HDM_DECODER0_CTRL_TYPE, ctrl) == 0) {

			struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);

			ctrl |= CXL_HDM_DECODER0_CTRL_TYPE;

			struct cxl_dev_state *cxlds = cxlmd->cxlds;



			/*

			 * Default by devtype until a device arrives that needs

			 * more precision.

			 */

			if (cxlds->type == CXL_DEVTYPE_CLASSMEM)

				cxld->target_type = CXL_DECODER_HOSTONLYMEM;

			else

				cxld->target_type = CXL_DECODER_DEVMEM;

		} else {

			/* To be overridden by region type at commit time */

			cxld->target_type = CXL_DECODER_HOSTONLYMEM;

		}



		if (!FIELD_GET(CXL_HDM_DECODER0_CTRL_HOSTONLY, ctrl) &&

		    cxld->target_type == CXL_DECODER_HOSTONLYMEM) {

			ctrl |= CXL_HDM_DECODER0_CTRL_HOSTONLY;

			writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which));

			writel(ctrl, hdm + CXL_HDM_DECODER0_CTRL_OFFSET(which));

		}

		}

		cxld->target_type = CXL_DECODER_HOSTONLYMEM;

	}

	}

	rc = eiw_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl),

	rc = eiw_to_ways(FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl),

			  &cxld->interleave_ways);

			  &cxld->interleave_ways);
@@ -881,7 +899,7 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, 
		port->id, cxld->id, cxld->hpa_range.start, cxld->hpa_range.end,

		port->id, cxld->id, cxld->hpa_range.start, cxld->hpa_range.end,

		cxld->interleave_ways, cxld->interleave_granularity);

		cxld->interleave_ways, cxld->interleave_granularity);





	if (!info) {

	if (!cxled) {

		lo = readl(hdm + CXL_HDM_DECODER0_TL_LOW(which));

		lo = readl(hdm + CXL_HDM_DECODER0_TL_LOW(which));

		hi = readl(hdm + CXL_HDM_DECODER0_TL_HIGH(which));

		hi = readl(hdm + CXL_HDM_DECODER0_TL_HIGH(which));

		target_list.value = (hi << 32) + lo;

		target_list.value = (hi << 32) + lo;
@@ -904,7 +922,6 @@ static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld, 
	lo = readl(hdm + CXL_HDM_DECODER0_SKIP_LOW(which));

	lo = readl(hdm + CXL_HDM_DECODER0_SKIP_LOW(which));

	hi = readl(hdm + CXL_HDM_DECODER0_SKIP_HIGH(which));

	hi = readl(hdm + CXL_HDM_DECODER0_SKIP_HIGH(which));

	skip = (hi << 32) + lo;

	skip = (hi << 32) + lo;

	cxled = to_cxl_endpoint_decoder(&cxld->dev);

	rc = devm_cxl_dpa_reserve(cxled, *dpa_base + skip, dpa_size, skip);

	rc = devm_cxl_dpa_reserve(cxled, *dpa_base + skip, dpa_size, skip);

	if (rc) {

	if (rc) {

		dev_err(&port->dev,

		dev_err(&port->dev,

drivers/cxl/cxl.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -56,7 +56,7 @@ 
#define   CXL_HDM_DECODER0_CTRL_COMMIT BIT(9)

#define   CXL_HDM_DECODER0_CTRL_COMMIT BIT(9)

#define   CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10)

#define   CXL_HDM_DECODER0_CTRL_COMMITTED BIT(10)

#define   CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11)

#define   CXL_HDM_DECODER0_CTRL_COMMIT_ERROR BIT(11)

#define   CXL_HDM_DECODER0_CTRL_TYPE BIT(12)

#define   CXL_HDM_DECODER0_CTRL_HOSTONLY BIT(12)

#define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24)

#define CXL_HDM_DECODER0_TL_LOW(i) (0x20 * (i) + 0x24)

#define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28)

#define CXL_HDM_DECODER0_TL_HIGH(i) (0x20 * (i) + 0x28)

#define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i)

#define CXL_HDM_DECODER0_SKIP_LOW(i) CXL_HDM_DECODER0_TL_LOW(i)