Commit ced3aaea authored by Taniya Das's avatar Taniya Das Committed by Stephen Boyd
Browse files

dt-bindings: clock: Add SC7280 DISPCC clock binding 



Add device tree bindings for display clock controller subsystem for
Qualcomm Technology Inc's SC7280 SoCs.

Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1626189143-12957-3-git-send-email-tdas@codeaurora.org


Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 8bde9dd3

Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Display Clock & Reset Controller Binding for SC7280



maintainers:

  - Taniya Das <tdas@codeaurora.org>



description: |

  Qualcomm display clock control module which supports the clocks, resets and

  power domains on SC7280.



  See also dt-bindings/clock/qcom,dispcc-sc7280.h.



properties:

  compatible:

    const: qcom,sc7280-dispcc



  clocks:

    items:

      - description: Board XO source

      - description: GPLL0 source from GCC

      - description: Byte clock from DSI PHY

      - description: Pixel clock from DSI PHY

      - description: Link clock from DP PHY

      - description: VCO DIV clock from DP PHY

      - description: Link clock from EDP PHY

      - description: VCO DIV clock from EDP PHY



  clock-names:

    items:

      - const: bi_tcxo

      - const: gcc_disp_gpll0_clk

      - const: dsi0_phy_pll_out_byteclk

      - const: dsi0_phy_pll_out_dsiclk

      - const: dp_phy_pll_link_clk

      - const: dp_phy_pll_vco_div_clk

      - const: edp_phy_pll_link_clk

      - const: edp_phy_pll_vco_div_clk



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sc7280.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@af00000 {

      compatible = "qcom,sc7280-dispcc";

      reg = <0x0af00000 0x200000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&gcc GCC_DISP_GPLL0_CLK_SRC>,

               <&dsi_phy 0>,

               <&dsi_phy 1>,

               <&dp_phy 0>,

               <&dp_phy 1>,

               <&edp_phy 0>,

               <&edp_phy 1>;

      clock-names = "bi_tcxo",

                    "gcc_disp_gpll0_clk",

                    "dsi0_phy_pll_out_byteclk",

                    "dsi0_phy_pll_out_dsiclk",

                    "dp_phy_pll_link_clk",

                    "dp_phy_pll_vco_div_clk",

                    "edp_phy_pll_link_clk",

                    "edp_phy_pll_vco_div_clk";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...

include/dt-bindings/clock/qcom,dispcc-sc7280.h

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2021, The Linux Foundation. All rights reserved.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H



/* DISP_CC clocks */

#define DISP_CC_PLL0					0

#define DISP_CC_MDSS_AHB_CLK				1

#define DISP_CC_MDSS_AHB_CLK_SRC			2

#define DISP_CC_MDSS_BYTE0_CLK				3

#define DISP_CC_MDSS_BYTE0_CLK_SRC			4

#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC			5

#define DISP_CC_MDSS_BYTE0_INTF_CLK			6

#define DISP_CC_MDSS_DP_AUX_CLK				7

#define DISP_CC_MDSS_DP_AUX_CLK_SRC			8

#define DISP_CC_MDSS_DP_CRYPTO_CLK			9

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC			10

#define DISP_CC_MDSS_DP_LINK_CLK			11

#define DISP_CC_MDSS_DP_LINK_CLK_SRC			12

#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC		13

#define DISP_CC_MDSS_DP_LINK_INTF_CLK			14

#define DISP_CC_MDSS_DP_PIXEL_CLK			15

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC			16

#define DISP_CC_MDSS_EDP_AUX_CLK			17

#define DISP_CC_MDSS_EDP_AUX_CLK_SRC			18

#define DISP_CC_MDSS_EDP_LINK_CLK			19

#define DISP_CC_MDSS_EDP_LINK_CLK_SRC			20

#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC		21

#define DISP_CC_MDSS_EDP_LINK_INTF_CLK			22

#define DISP_CC_MDSS_EDP_PIXEL_CLK			23

#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC			24

#define DISP_CC_MDSS_ESC0_CLK				25

#define DISP_CC_MDSS_ESC0_CLK_SRC			26

#define DISP_CC_MDSS_MDP_CLK				27

#define DISP_CC_MDSS_MDP_CLK_SRC			28

#define DISP_CC_MDSS_MDP_LUT_CLK			29

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK			30

#define DISP_CC_MDSS_PCLK0_CLK				31

#define DISP_CC_MDSS_PCLK0_CLK_SRC			32

#define DISP_CC_MDSS_ROT_CLK				33

#define DISP_CC_MDSS_ROT_CLK_SRC			34

#define DISP_CC_MDSS_RSCC_AHB_CLK			35

#define DISP_CC_MDSS_RSCC_VSYNC_CLK			36

#define DISP_CC_MDSS_VSYNC_CLK				37

#define DISP_CC_MDSS_VSYNC_CLK_SRC			38

#define DISP_CC_SLEEP_CLK				39

#define DISP_CC_XO_CLK					40



/* DISP_CC power domains */

#define DISP_CC_MDSS_CORE_GDSC				0



#endif