Commit cf689e86 authored by Melissa Wen's avatar Melissa Wen Committed by Alex Deucher
Browse files

drm/amd/display: move FPU-related code from dcn20 to dml folder 

Move parts of dcn20 code that uses FPU to dml folder. It aims to isolate
FPU operations as described by series:

drm/amd/display: Introduce FPU directory inside DC
https://patchwork.freedesktop.org/series/93042/



This patch moves the following functions from dcn20_resource to
dml/dcn20_fpu and calls of public functions in dcn20_resource are
wrapped by DC_FP_START/END():

- void dcn20_populate_dml_writeback_from_context
- static bool is_dtbclk_required()
- static enum dcn_zstate_support_state()
- void dcn20_calculate_dlg_params()
- static void swizzle_to_dml_params()
- int dcn20_populate_dml_pipes_from_context()
- void dcn20_calculate_wm()
- void dcn20_cap_soc_clocks()
- void dcn20_update_bounding_box()
- void dcn20_patch_bounding_box()
- bool dcn20_validate_bandwidth_fp()

This movement also affects dcn21/30/31, as dcn20_calculate_dlg_params()
is used by them. For this reason, I included dcn20_fpu headers in
dcn20_resource headers to make dcn20_calculate_dlg_params() visible to
dcn21/30/31.

Three new functions are created to isolate well-delimited FPU
operations:

- void dcn20_fpu_set_wb_arb_params(): set cli_watermark,
  pstate_watermark and time_per_pixel from wb_arb_params (struct
mcif_arb_params), since those uses FPU operations on double types:
WritebackUrgentWatermark, WritebackDRAMClockChangeWatermark, '16.0'.
- void dcn20_fpu_set_wm_ranges(): set min_fill_clk_mhz and
  max_fill_clk_mhz involves FPU calcs on dram_speed_mts (double type);
- void dcn20_fpu_adjust_dppclk(): adjust operation on RequiredDPPCLK
  that is a double.

Signed-off-by: default avatarMelissa Wen <mwen@igalia.com>
Acked-by: default avatarAlan Liu <HaoPing.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 44ca49f0

drivers/gpu/drm/amd/display/dc/dcn20/Makefile

+0 −25
Original line number Diff line number Diff line
@@ -9,31 +9,6 @@ DCN20 = dcn20_resource.o dcn20_init.o dcn20_hwseq.o dcn20_dpp.o dcn20_dpp_cm.o d 


DCN20 += dcn20_dsc.o



ifdef CONFIG_X86

CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -msse

endif



ifdef CONFIG_PPC64

CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o := -mhard-float -maltivec

endif



ifdef CONFIG_CC_IS_GCC

ifeq ($(call cc-ifversion, -lt, 0701, y), y)

IS_OLD_GCC = 1

endif

endif



ifdef CONFIG_X86

ifdef IS_OLD_GCC

# Stack alignment mismatch, proceed with caution.

# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3

# (8B stack alignment).

CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -mpreferred-stack-boundary=4

else

CFLAGS_$(AMDDALPATH)/dc/dcn20/dcn20_resource.o += -msse2

endif

endif



AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))



AMD_DISPLAY_FILES += $(AMD_DAL_DCN20)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+18 −1351

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h

+8 −23
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#define __DC_RESOURCE_DCN20_H__



#include "core_types.h"

#include "dml/dcn20/dcn20_fpu.h"



#define TO_DCN20_RES_POOL(pool)\

	container_of(pool, struct dcn20_resource_pool, base)
@@ -35,6 +36,12 @@ struct dc; 
struct resource_pool;

struct _vcs_dpi_display_pipe_params_st;



extern struct _vcs_dpi_ip_params_st dcn2_0_ip;

extern struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip;

extern struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc;

extern struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc;

extern struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc;



struct dcn20_resource_pool {

	struct resource_pool base;

};
@@ -49,11 +56,7 @@ unsigned int dcn20_calc_max_scaled_time( 
		unsigned int time_per_pixel,

		enum mmhubbub_wbif_mode mode,

		unsigned int urgent_watermark);

int dcn20_populate_dml_pipes_from_context(

		struct dc *dc,

		struct dc_state *context,

		display_e2e_pipe_params_st *pipes,

		bool fast_validate);



struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(

		struct dc_state *state,

		const struct resource_pool *pool,
@@ -79,7 +82,6 @@ struct dpp *dcn20_dpp_create( 
struct input_pixel_processor *dcn20_ipp_create(

	struct dc_context *ctx, uint32_t inst);





struct output_pixel_processor *dcn20_opp_create(

	struct dc_context *ctx, uint32_t inst);
@@ -96,11 +98,6 @@ struct display_stream_compressor *dcn20_dsc_create( 
	struct dc_context *ctx, uint32_t inst);

void dcn20_dsc_destroy(struct display_stream_compressor **dsc);



void dcn20_cap_soc_clocks(

		struct _vcs_dpi_soc_bounding_box_st *bb,

		struct pp_smu_nv_clock_table max_clocks);

void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,

		struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states);

struct hubp *dcn20_hubp_create(

	struct dc_context *ctx,

	uint32_t inst);
@@ -158,11 +155,6 @@ bool dcn20_fast_validate_bw( 
		int *pipe_split_from,

		int *vlevel_out,

		bool fast_validate);

void dcn20_calculate_dlg_params(

		struct dc *dc, struct dc_state *context,

		display_e2e_pipe_params_st *pipes,

		int pipe_cnt,

		int vlevel);



enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream);

enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);
@@ -170,12 +162,5 @@ enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state * 
enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream);

enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state);



void dcn20_patch_bounding_box(

		struct dc *dc,

		struct _vcs_dpi_soc_bounding_box_st *bb);

void dcn20_cap_soc_clocks(

		struct _vcs_dpi_soc_bounding_box_st *bb,

		struct pp_smu_nv_clock_table max_clocks);



#endif /* __DC_RESOURCE_DCN20_H__ */

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

+7 −1
Original line number Diff line number Diff line
@@ -1363,7 +1363,9 @@ static noinline bool dcn21_validate_bandwidth_fp(struct dc *dc, 
	}



	dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);

	DC_FP_START();

	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

	DC_FP_END();



	BW_VAL_TRACE_END_WATERMARKS();
@@ -1902,9 +1904,13 @@ static int dcn21_populate_dml_pipes_from_context( 
		display_e2e_pipe_params_st *pipes,

		bool fast_validate)

{

	uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);

	uint32_t pipe_cnt;

	int i;



	DC_FP_START();

	pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);

	DC_FP_END();



	for (i = 0; i < pipe_cnt; i++) {



		pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

+7 −0
Original line number Diff line number Diff line
@@ -1462,7 +1462,9 @@ int dcn30_populate_dml_pipes_from_context( 
	int i, pipe_cnt;

	struct resource_context *res_ctx = &context->res_ctx;



	DC_FP_START();

	dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);

	DC_FP_END();



	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {

		if (!res_ctx->pipe_ctx[i].stream)
@@ -1731,7 +1733,10 @@ static bool init_soc_bounding_box(struct dc *dc, 
	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;

	loaded_ip->max_num_dpp = pool->base.pipe_count;

	loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;



	DC_FP_START();

	dcn20_patch_bounding_box(dc, loaded_bb);

	DC_FP_END();



	if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

		struct bp_soc_bb_info bb_info = {0};
@@ -2261,7 +2266,9 @@ static noinline void dcn30_calculate_wm_and_dlg_fp( 
		pipe_idx++;

	}



	DC_FP_START();

	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

	DC_FP_END();



	if (!pstate_en)

		/* Restore full p-state latency */