Commit cf7b8b80 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
Browse files

rtw89: update STA scheduler parameters for v1 chip 



The v1 chip has additional setting of STA scheduler, so add it.

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220325060055.58482-10-pkshih@realtek.com
parent a7d82a7a

drivers/net/wireless/realtek/rtw89/mac.c

+15 −1
Original line number Original line Diff line number Diff line
@@ -1560,6 +1560,17 @@ static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 
	return false;

	return false;

}

}





static void _patch_ss2f_path(struct rtw89_dev *rtwdev)

{

	const struct rtw89_chip_info *chip = rtwdev->chip;



	if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B)

		return;



	rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK,

			   SS2F_PATH_WLCPU);

}



static int sta_sch_init(struct rtw89_dev *rtwdev)

static int sta_sch_init(struct rtw89_dev *rtwdev)

{

{

	u32 p_val;

	u32 p_val;
@@ -1581,7 +1592,10 @@ static int sta_sch_init(struct rtw89_dev *rtwdev) 
		return ret;

		return ret;

	}

	}





	rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG);

	rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG |

						B_AX_SS_NONEMPTY_SS2FINFO_EN);



	_patch_ss2f_path(rtwdev);





	return 0;

	return 0;

}

}

drivers/net/wireless/realtek/rtw89/reg.h

+9 −0
Original line number Original line Diff line number Diff line
@@ -801,8 +801,17 @@ 
#define R_AX_SS_CTRL 0x9E10

#define R_AX_SS_CTRL 0x9E10

#define B_AX_SS_INIT_DONE_1 BIT(31)

#define B_AX_SS_INIT_DONE_1 BIT(31)

#define B_AX_SS_WARM_INIT_FLG BIT(29)

#define B_AX_SS_WARM_INIT_FLG BIT(29)

#define B_AX_SS_NONEMPTY_SS2FINFO_EN BIT(28)

#define B_AX_SS_EN BIT(0)

#define B_AX_SS_EN BIT(0)





#define R_AX_SS2FINFO_PATH 0x9E50

#define B_AX_SS_UL_REL BIT(31)

#define B_AX_SS_REL_QUEUE_MASK GENMASK(29, 24)

#define B_AX_SS_REL_PORT_MASK GENMASK(18, 16)

#define B_AX_SS_DEST_QUEUE_MASK GENMASK(13, 8)

#define SS2F_PATH_WLCPU 0x0A

#define B_AX_SS_DEST_PORT_MASK GENMASK(2, 0)



#define R_AX_SS_MACID_PAUSE_0 0x9EB0

#define R_AX_SS_MACID_PAUSE_0 0x9EB0

#define B_AX_SS_MACID31_0_PAUSE_SH 0

#define B_AX_SS_MACID31_0_PAUSE_SH 0

#define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)

#define B_AX_SS_MACID31_0_PAUSE_MASK GENMASK(31, 0)