Commit cfebd007 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Dave Hansen
Browse files

x86/apic: Consolidate wait_icr_idle() implementations 



Two copies and also needlessly public. Move it into ipi.c so it can be
inlined. Rename it to apic_mem_wait_icr_idle().

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: default avatarMichael Kelley <mikelley@microsoft.com>
Tested-by: default avatarSohil Mehta <sohil.mehta@intel.com>
Tested-by: Juergen Gross <jgross@suse.com> # Xen PV (dom0 and unpriv. guest)
parent 01363d4f

arch/x86/include/asm/apic.h

+0 −1
Original line number Diff line number Diff line
@@ -98,7 +98,6 @@ static inline u32 native_apic_mem_read(u32 reg) 
	return *((volatile u32 *)(APIC_BASE + reg));

}



extern void native_apic_wait_icr_idle(void);

extern u32 native_safe_apic_wait_icr_idle(void);

extern void native_apic_icr_write(u32 low, u32 id);

extern u64 native_apic_icr_read(void);

arch/x86/kernel/apic/apic.c

+0 −6
Original line number Diff line number Diff line
@@ -240,12 +240,6 @@ static void __init apic_disable(void) 
	apic = &apic_noop;

}



void native_apic_wait_icr_idle(void)

{

	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)

		cpu_relax();

}



u32 native_safe_apic_wait_icr_idle(void)

{

	u32 send_status;

arch/x86/kernel/apic/apic_flat_64.c

+2 −2
Original line number Diff line number Diff line
@@ -111,7 +111,7 @@ static struct apic apic_flat __ro_after_init = { 
	.eoi_write			= native_apic_mem_write,

	.icr_read			= native_apic_icr_read,

	.icr_write			= native_apic_icr_write,

	.wait_icr_idle			= native_apic_wait_icr_idle,

	.wait_icr_idle			= apic_mem_wait_icr_idle,

	.safe_wait_icr_idle		= native_safe_apic_wait_icr_idle,

};
@@ -187,7 +187,7 @@ static struct apic apic_physflat __ro_after_init = { 
	.eoi_write			= native_apic_mem_write,

	.icr_read			= native_apic_icr_read,

	.icr_write			= native_apic_icr_write,

	.wait_icr_idle			= native_apic_wait_icr_idle,

	.wait_icr_idle			= apic_mem_wait_icr_idle,

	.safe_wait_icr_idle		= native_safe_apic_wait_icr_idle,

};

arch/x86/kernel/apic/bigsmp_32.c

+1 −1
Original line number Diff line number Diff line
@@ -108,7 +108,7 @@ static struct apic apic_bigsmp __ro_after_init = { 
	.eoi_write			= native_apic_mem_write,

	.icr_read			= native_apic_icr_read,

	.icr_write			= native_apic_icr_write,

	.wait_icr_idle			= native_apic_wait_icr_idle,

	.wait_icr_idle			= apic_mem_wait_icr_idle,

	.safe_wait_icr_idle		= native_safe_apic_wait_icr_idle,

};

arch/x86/kernel/apic/ipi.c

+3 −3
Original line number Diff line number Diff line
@@ -102,7 +102,7 @@ static inline int __prepare_ICR2(unsigned int mask) 
	return SET_XAPIC_DEST_FIELD(mask);

}



static inline void __xapic_wait_icr_idle(void)

void apic_mem_wait_icr_idle(void)

{

	while (native_apic_mem_read(APIC_ICR) & APIC_ICR_BUSY)

		cpu_relax();
@@ -137,7 +137,7 @@ static void __default_send_IPI_shortcut(unsigned int shortcut, int vector) 
	if (unlikely(vector == NMI_VECTOR))

		safe_apic_wait_icr_idle();

	else

		__xapic_wait_icr_idle();

		apic_mem_wait_icr_idle();



	/* Destination field (ICR2) and the destination mode are ignored */

	native_apic_mem_write(APIC_ICR, __prepare_ICR(shortcut, vector, 0));
@@ -154,7 +154,7 @@ void __default_send_IPI_dest_field(unsigned int dest_mask, int vector, 
	if (unlikely(vector == NMI_VECTOR))

		safe_apic_wait_icr_idle();

	else

		__xapic_wait_icr_idle();

		apic_mem_wait_icr_idle();



	/* Set the IPI destination field in the ICR */

	native_apic_mem_write(APIC_ICR2, __prepare_ICR2(dest_mask));