Commit d4a37561 authored by Thippeswamy Havalige's avatar Thippeswamy Havalige Committed by Michal Simek
Browse files

microblaze/PCI: Remove unused PCI Indirect ops 



Remove unused variants of PCI indirect handling.

Signed-off-by: default avatarThippeswamy Havalige <thippeswamy.havalige@amd.com>
Link: https://lore.kernel.org/r/20221025065214.4663-9-thippeswamy.havalige@amd.com


Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
parent 7df700af

arch/microblaze/include/asm/pci-bridge.h

+0 −34
Original line number Diff line number Diff line
@@ -32,8 +32,6 @@ struct pci_controller { 
	int first_busno;

	int last_busno;



	int self_busno;



	void __iomem *io_base_virt;

	resource_size_t io_base_phys;
@@ -42,34 +40,6 @@ struct pci_controller { 
	 */

	resource_size_t pci_mem_offset;



	struct pci_ops *ops;

	unsigned int __iomem *cfg_addr;

	void __iomem *cfg_data;



	/*

	 * Used for variants of PCI indirect handling and possible quirks:

	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1

	 *  EXT_REG - provides access to PCI-e extended registers

	 *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS

	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS

	 *   to determine which bus number to match on when generating type0

	 *   config cycles

	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with

	 *   hanging if we don't have link and try to do config cycles to

	 *   anything but the PHB.  Only allow talking to the PHB if this is

	 *   set.

	 *  BIG_ENDIAN - cfg_addr is a big endian register

	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs

	 *   on the PLB4.  Effectively disable MRM commands by setting this.

	 */

#define INDIRECT_TYPE_SET_CFG_TYPE		0x00000001

#define INDIRECT_TYPE_EXT_REG		0x00000002

#define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004

#define INDIRECT_TYPE_NO_PCIE_LINK		0x00000008

#define INDIRECT_TYPE_BIG_ENDIAN		0x00000010

#define INDIRECT_TYPE_BROKEN_MRM		0x00000020

	u32 indirect_type;



	/* Currently, we limit ourselves to 1 IO range and 3 mem

	 * ranges since the common pci_bus structure can't handle more

	 */
@@ -91,9 +61,5 @@ static inline int isa_vaddr_is_ioport(void __iomem *address) 
}

#endif /* CONFIG_PCI */



extern void setup_indirect_pci(struct pci_controller *hose,

			       resource_size_t cfg_addr,

			       resource_size_t cfg_data, u32 flags);



#endif	/* __KERNEL__ */

#endif	/* _ASM_MICROBLAZE_PCI_BRIDGE_H */

arch/microblaze/pci/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -3,5 +3,5 @@ 
# Makefile

#



obj-$(CONFIG_PCI)		+= pci-common.o indirect_pci.o iomap.o

obj-$(CONFIG_PCI)		+= pci-common.o iomap.o

obj-$(CONFIG_PCI_XILINX)	+= xilinx_pci.o

arch/microblaze/pci/indirect_pci.c

deleted100644 → 0
+0 −158
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-or-later

/*

 * Support for indirect PCI bridges.

 *

 * Copyright (C) 1998 Gabriel Paubert.

 */



#include <linux/kernel.h>

#include <linux/pci.h>

#include <linux/delay.h>

#include <linux/string.h>

#include <linux/init.h>



#include <linux/io.h>

#include <asm/pci-bridge.h>



static int

indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,

		     int len, u32 *val)

{

	struct pci_controller *hose = pci_bus_to_host(bus);

	volatile void __iomem *cfg_data;

	u8 cfg_type = 0;

	u32 bus_no, reg;



	if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {

		if (bus->number != hose->first_busno)

			return PCIBIOS_DEVICE_NOT_FOUND;

		if (devfn != 0)

			return PCIBIOS_DEVICE_NOT_FOUND;

	}



	if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)

		if (bus->number != hose->first_busno)

			cfg_type = 1;



	bus_no = (bus->number == hose->first_busno) ?

			hose->self_busno : bus->number;



	if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)

		reg = ((offset & 0xf00) << 16) | (offset & 0xfc);

	else

		reg = offset & 0xfc; /* Only 3 bits for function */



	if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)

		out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |

			 (devfn << 8) | reg | cfg_type));

	else

		out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |

			 (devfn << 8) | reg | cfg_type));



	/*

	 * Note: the caller has already checked that offset is

	 * suitably aligned and that len is 1, 2 or 4.

	 */

	cfg_data = hose->cfg_data + (offset & 3); /* Only 3 bits for function */

	switch (len) {

	case 1:

		*val = in_8(cfg_data);

		break;

	case 2:

		*val = in_le16(cfg_data);

		break;

	default:

		*val = in_le32(cfg_data);

		break;

	}

	return PCIBIOS_SUCCESSFUL;

}



static int

indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,

		      int len, u32 val)

{

	struct pci_controller *hose = pci_bus_to_host(bus);

	volatile void __iomem *cfg_data;

	u8 cfg_type = 0;

	u32 bus_no, reg;



	if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {

		if (bus->number != hose->first_busno)

			return PCIBIOS_DEVICE_NOT_FOUND;

		if (devfn != 0)

			return PCIBIOS_DEVICE_NOT_FOUND;

	}



	if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE)

		if (bus->number != hose->first_busno)

			cfg_type = 1;



	bus_no = (bus->number == hose->first_busno) ?

			hose->self_busno : bus->number;



	if (hose->indirect_type & INDIRECT_TYPE_EXT_REG)

		reg = ((offset & 0xf00) << 16) | (offset & 0xfc);

	else

		reg = offset & 0xfc;



	if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN)

		out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |

			 (devfn << 8) | reg | cfg_type));

	else

		out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |

			 (devfn << 8) | reg | cfg_type));



	/* suppress setting of PCI_PRIMARY_BUS */

	if (hose->indirect_type & INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)

		if ((offset == PCI_PRIMARY_BUS) &&

			(bus->number == hose->first_busno))

			val &= 0xffffff00;



	/* Workaround for PCI_28 Errata in 440EPx/GRx */

	if ((hose->indirect_type & INDIRECT_TYPE_BROKEN_MRM) &&

			offset == PCI_CACHE_LINE_SIZE) {

		val = 0;

	}



	/*

	 * Note: the caller has already checked that offset is

	 * suitably aligned and that len is 1, 2 or 4.

	 */

	cfg_data = hose->cfg_data + (offset & 3);

	switch (len) {

	case 1:

		out_8(cfg_data, val);

		break;

	case 2:

		out_le16(cfg_data, val);

		break;

	default:

		out_le32(cfg_data, val);

		break;

	}



	return PCIBIOS_SUCCESSFUL;

}



static struct pci_ops indirect_pci_ops = {

	.read = indirect_read_config,

	.write = indirect_write_config,

};



void __init

setup_indirect_pci(struct pci_controller *hose,

		   resource_size_t cfg_addr,

		   resource_size_t cfg_data, u32 flags)

{

	resource_size_t base = cfg_addr & PAGE_MASK;

	void __iomem *mbase;



	mbase = ioremap(base, PAGE_SIZE);

	hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);

	if ((cfg_data & PAGE_MASK) != base)

		mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);

	hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);

	hose->ops = &indirect_pci_ops;

	hose->indirect_type = flags;

}

arch/microblaze/pci/xilinx_pci.c

+0 −6
Original line number Diff line number Diff line
@@ -83,7 +83,6 @@ xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn) 
 */

void __init xilinx_pci_init(void)

{

	struct pci_controller *hose;

	struct resource r;

	void __iomem *pci_reg;

	struct device_node *pci_node;
@@ -97,11 +96,6 @@ void __init xilinx_pci_init(void) 
		return;

	}



	/* Setup config space */

	setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,

			   r.start + XPLB_PCI_DATA,

			   INDIRECT_TYPE_SET_CFG_TYPE);



	/* Set the max bus number to 255, and bus/subbus no's to 0 */

	pci_reg = of_iomap(pci_node, 0);

	WARN_ON(!pci_reg);