Commit d55b1ecc authored Nov 23, 2021 by Nicholas Piggin Committed by Michael Ellerman Nov 24, 2021

KVM: PPC: Book3S HV P9: Restrict DSISR canary workaround to processors that require it

Use CPU_FTR_P9_RADIX_PREFETCH_BUG to apply the workaround, to test for
DD2.1 and below processors. This saves a mtSPR in guest entry.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211123095231.1036501-35-npiggin@gmail.com

parent 3e7b3379

arch/powerpc/kvm/book3s_hv.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -1590,7 +1590,8 @@ static int kvmppc_handle_exit_hv(struct kvm_vcpu *vcpu,
		unsigned long vsid;
		long err;

		if (vcpu->arch.fault_dsisr == HDSISR_CANARY) {
		if (cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG) &&
		unlikely(vcpu->arch.fault_dsisr == HDSISR_CANARY)) {
		r = RESUME_GUEST; /* Just retry if it's the canary */
		break;
		}

arch/powerpc/kvm/book3s_hv_p9_entry.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -683,8 +683,10 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc
		* HDSI which should correctly update the HDSISR the second time HDSI
		* entry.
		*
		* Just do this on all p9 processors for now.
		* The "radix prefetch bug" test can be used to test for this bug, as
		* it also exists fo DD2.1 and below.
		*/
		if (cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG))
		mtspr(SPRN_HDSISR, HDSISR_CANARY);

		mtspr(SPRN_SPRG0, vcpu->arch.shregs.sprg0);