Commit d5bec403 authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Use DCC meta pitch for MALL allocation requirements 



[Description]
Calculations for determining DCC meta size should be pitch*height*bpp/256.

Reviewed-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: default avatarJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: default avatarDillon Varone <Dillon.Varone@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 359bcc90

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

+3 −3
Original line number Diff line number Diff line
@@ -263,10 +263,10 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *c 
				((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height);



		/*For DCC:

		 * meta_num_mblk = CEILING(full_mblk_width_ub_l*full_mblk_height_ub_l*Bpe/256/mblk_bytes, 1)

		 * meta_num_mblk = CEILING(meta_pitch*full_vp_height*Bpe/256/mblk_bytes, 1)

		 */

		if (pipe->plane_state->dcc.enable)

			num_mblks += (mall_alloc_width_blk_aligned * mall_alloc_width_blk_aligned * bytes_per_pixel +

			num_mblks += (pipe->plane_state->dcc.meta_pitch * pipe->plane_res.scl_data.viewport.height * bytes_per_pixel +

					(256 * DCN3_2_MALL_MBLK_SIZE_BYTES) - 1) / (256 * DCN3_2_MALL_MBLK_SIZE_BYTES);



		bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES;

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c

+8 −3
Original line number Diff line number Diff line
@@ -121,14 +121,19 @@ uint32_t dcn32_helper_calculate_num_ways_for_subvp(struct dc *dc, struct dc_stat 
			 */

			num_mblks = ((mall_alloc_width_blk_aligned + mblk_width - 1) / mblk_width) *

					((mall_alloc_height_blk_aligned + mblk_height - 1) / mblk_height);



			/*For DCC:

			 * meta_num_mblk = CEILING(meta_pitch*full_vp_height*Bpe/256/mblk_bytes, 1)

			 */

			if (pipe->plane_state->dcc.enable)

				num_mblks += (pipe->plane_state->dcc.meta_pitch * pipe->plane_res.scl_data.viewport.height * bytes_per_pixel +

								(256 * DCN3_2_MALL_MBLK_SIZE_BYTES) - 1) / (256 * DCN3_2_MALL_MBLK_SIZE_BYTES);



			bytes_in_mall = num_mblks * DCN3_2_MALL_MBLK_SIZE_BYTES;

			// cache lines used is total bytes / cache_line size. Add +2 for worst case alignment

			// (MALL is 64-byte aligned)

			cache_lines_per_plane = bytes_in_mall / dc->caps.cache_line_size + 2;



			/* For DCC divide by 256 */

			if (pipe->plane_state->dcc.enable)

				cache_lines_per_plane = cache_lines_per_plane + (cache_lines_per_plane / 256) + 1;

			cache_lines_used += cache_lines_per_plane;

		}

	}