Commit d5fb01ad authored by Luca Weiss's avatar Luca Weiss Committed by Bjorn Andersson
Browse files

ARM: dts: qcom: msm8226: Add mdss nodes 



Add the nodes that describe the mdss so that display can work on
MSM8226.

Signed-off-by: default avatarLuca Weiss <luca@z3ntu.xyz>
Link: https://lore.kernel.org/r/20230308-msm8226-mdp-v3-7-b6284145d67a@z3ntu.xyz


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 06c2afb8

arch/arm/boot/dts/qcom/qcom-msm8226.dtsi

+127 −0
Original line number Diff line number Diff line
@@ -797,6 +797,133 @@ reboot-mode { 
				mode-recovery   = <0x77665502>;

			};

		};



		mdss: display-subsystem@fd900000 {

			compatible = "qcom,mdss";

			reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;

			reg-names = "mdss_phys", "vbif_phys";



			power-domains = <&mmcc MDSS_GDSC>;



			clocks = <&mmcc MDSS_AHB_CLK>,

				 <&mmcc MDSS_AXI_CLK>,

				 <&mmcc MDSS_VSYNC_CLK>;

			clock-names = "iface",

				      "bus",

				      "vsync";



			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;



			interrupt-controller;

			#interrupt-cells = <1>;



			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			status = "disabled";



			mdss_mdp: display-controller@fd900000 {

				compatible = "qcom,msm8226-mdp5", "qcom,mdp5";

				reg = <0xfd900100 0x22000>;

				reg-names = "mdp_phys";



				interrupt-parent = <&mdss>;

				interrupts = <0>;



				clocks = <&mmcc MDSS_AHB_CLK>,

					 <&mmcc MDSS_AXI_CLK>,

					 <&mmcc MDSS_MDP_CLK>,

					 <&mmcc MDSS_VSYNC_CLK>;

				clock-names = "iface",

					      "bus",

					      "core",

					      "vsync";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						mdss_mdp_intf1_out: endpoint {

							remote-endpoint = <&mdss_dsi0_in>;

						};

					};

				};

			};



			mdss_dsi0: dsi@fd922800 {

				compatible = "qcom,msm8226-dsi-ctrl",

					     "qcom,mdss-dsi-ctrl";

				reg = <0xfd922800 0x1f8>;

				reg-names = "dsi_ctrl";



				interrupt-parent = <&mdss>;

				interrupts = <4>;



				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,

						  <&mmcc PCLK0_CLK_SRC>;

				assigned-clock-parents = <&mdss_dsi0_phy 0>,

							 <&mdss_dsi0_phy 1>;



				clocks = <&mmcc MDSS_MDP_CLK>,

					 <&mmcc MDSS_AHB_CLK>,

					 <&mmcc MDSS_AXI_CLK>,

					 <&mmcc MDSS_BYTE0_CLK>,

					 <&mmcc MDSS_PCLK0_CLK>,

					 <&mmcc MDSS_ESC0_CLK>,

					 <&mmcc MMSS_MISC_AHB_CLK>;

				clock-names = "mdp_core",

					      "iface",

					      "bus",

					      "byte",

					      "pixel",

					      "core",

					      "core_mmss";



				phys = <&mdss_dsi0_phy>;



				#address-cells = <1>;

				#size-cells = <0>;



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						mdss_dsi0_in: endpoint {

							remote-endpoint = <&mdss_mdp_intf1_out>;

						};

					};



					port@1 {

						reg = <1>;

						mdss_dsi0_out: endpoint {

						};

					};

				};

			};



			mdss_dsi0_phy: phy@fd922a00 {

				compatible = "qcom,dsi-phy-28nm-8226";

				reg = <0xfd922a00 0xd4>,

				      <0xfd922b00 0x280>,

				      <0xfd922d80 0x30>;

				reg-names = "dsi_pll",

					    "dsi_phy",

					    "dsi_phy_regulator";



				#clock-cells = <1>;

				#phy-cells = <0>;



				clocks = <&mmcc MDSS_AHB_CLK>,

					 <&rpmcc RPM_SMD_XO_CLK_SRC>;

				clock-names = "iface",

					      "ref";

			};

		};

	};



	thermal-zones {