Commit d68f50e6 authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Sylwester Nawrocki
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dt-bindings: clock: samsung: add IDs for some core clocks 



Add IDs for some core clocks referenced during the boot process.

Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20211018125456.8292-1-m.szyprowski@samsung.com


Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent fa55b7dc

include/dt-bindings/clock/exynos4.h

+3 −1
Original line number Diff line number Diff line
@@ -209,6 +209,7 @@ 
#define CLK_ACLK400_MCUISP	395 /* Exynos4x12 only */

#define CLK_MOUT_HDMI		396

#define CLK_MOUT_MIXER		397

#define CLK_MOUT_VPLLSRC	398



/* gate clocks - ppmu */

#define CLK_PPMULEFT		400
@@ -236,9 +237,10 @@ 
#define CLK_DIV_C2C		458 /* Exynos4x12 only */

#define CLK_DIV_GDL		459

#define CLK_DIV_GDR		460

#define CLK_DIV_CORE2		461



/* must be greater than maximal clock id */

#define CLK_NR_CLKS		461

#define CLK_NR_CLKS		462



/* Exynos4x12 ISP clocks */

#define CLK_ISP_FIMC_ISP		 1

include/dt-bindings/clock/exynos5250.h

+3 −1
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ 
#define CLK_FOUT_EPLL		7

#define CLK_FOUT_VPLL		8

#define CLK_ARM_CLK		9

#define CLK_DIV_ARM2		10



/* gate for special clocks (sclk) */

#define CLK_SCLK_CAM_BAYER	128
@@ -174,8 +175,9 @@ 
#define CLK_MOUT_ACLK300_DISP1_SUB	1027

#define CLK_MOUT_APLL		1028

#define CLK_MOUT_MPLL		1029

#define CLK_MOUT_VPLLSRC	1030



/* must be greater than maximal clock id */

#define CLK_NR_CLKS		1030

#define CLK_NR_CLKS		1031



#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */