Commit d71dac3b authored by Miquel Raynal's avatar Miquel Raynal
Browse files

Merge tag 'mtd/spi-mem-ecc-for-5.18' into mtd/next 

Topic branch bringing-in changes related to the support of ECC engines
that can be used by SPI controllers to manage SPI NANDs as well as
possibly by parallel NAND controllers. In particular, it brings support
for Macronix ECC engine that can be used with Macronix SPI controller.

The changes touch the NAND core, the NAND ECC core, the spi-mem layer, a
SPI controller driver and add a new NAND ECC driver, as well as a number
of binding updates.

Binding changes:
* Vendor prefixes: Clarify Macronix prefix
* SPI NAND: Convert spi-nand description file to yaml
* Raw NAND chip: Create a NAND chip description
* Raw NAND controller:
  - Harmonize the property types
  - Fix a comment in the examples
  - Fix the reg property description
* Describe Macronix NAND ECC engine
* Macronix SPI controller:
  - Document the nand-ecc-engine property
  - Convert to yaml
  - The interrupt property is not mandatory

NAND core changes:
* ECC:
  - Add infrastructure to support hardware engines
  - Add a new helper to retrieve the ECC context
  - Provide a helper to retrieve a pilelined engine device

NAND-ECC changes:
* Macronix ECC engine:
  - Add Macronix external ECC engine support
  - Support SPI pipelined mode

SPI-NAND core changes:
* Delay a little bit the dirmap creation
* Create direct mapping descriptors for ECC operations

SPI-NAND driver changes:
* macronix: Use random program load

SPI changes:
* Macronix SPI controller:
  - Fix the transmit path
  - Create a helper to configure the controller before an operation
  - Create a helper to ease the start of an operation
  - Add support for direct mapping
  - Add support for pipelined ECC operations
* spi-mem:
  - Introduce a capability structure
  - Check the controller extra capabilities
  - cadence-quadspi/mxic: Provide capability structures
  - Kill the spi_mem_dtr_supports_op() helper
  - Add an ecc parameter to the spi_mem_op structure
parents ad5e35f5 00360eba

Documentation/devicetree/bindings/mtd/mxicy,nand-ecc-engine.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Macronix NAND ECC engine device tree bindings



maintainers:

  - Miquel Raynal <miquel.raynal@bootlin.com>



properties:

  compatible:

    const: mxicy,nand-ecc-engine-rev3



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    /* External configuration */

    spi_controller0: spi@43c30000 {

        compatible = "mxicy,mx25f0a-spi";

        reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;

        reg-names = "regs", "dirmap";

        clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;

        clock-names = "send_clk", "send_dly_clk", "ps_clk";

        #address-cells = <1>;

        #size-cells = <0>;



        flash@0 {

            compatible = "spi-nand";

            reg = <0>;

            nand-ecc-engine = <&ecc_engine0>;

        };

    };



    ecc_engine0: ecc@43c40000 {

        compatible = "mxicy,nand-ecc-engine-rev3";

        reg = <0x43c40000 0x10000>;

    };



  - |

    /* Pipelined configuration */

    spi_controller1: spi@43c30000 {

        compatible = "mxicy,mx25f0a-spi";

        reg = <0x43c30000 0x10000>, <0xa0000000 0x4000000>;

        reg-names = "regs", "dirmap";

        clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;

        clock-names = "send_clk", "send_dly_clk", "ps_clk";

        #address-cells = <1>;

        #size-cells = <0>;

        nand-ecc-engine = <&ecc_engine1>;



        flash@0 {

            compatible = "spi-nand";

            reg = <0>;

            nand-ecc-engine = <&spi_controller1>;

        };

    };



    ecc_engine1: ecc@43c40000 {

        compatible = "mxicy,nand-ecc-engine-rev3";

        reg = <0x43c40000 0x10000>;

    };

Documentation/devicetree/bindings/mtd/nand-chip.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/nand-chip.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NAND Chip and NAND Controller Generic Binding



maintainers:

  - Miquel Raynal <miquel.raynal@bootlin.com>



description: |

  This file covers the generic description of a NAND chip. It implies that the

  bus interface should not be taken into account: both raw NAND devices and

  SPI-NAND devices are concerned by this description.



properties:

  reg:

    description:

      Contains the chip-select IDs.



  nand-ecc-engine:

    description: |

      A phandle on the hardware ECC engine if any. There are

      basically three possibilities:

      1/ The ECC engine is part of the NAND controller, in this

      case the phandle should reference the parent node.

      2/ The ECC engine is part of the NAND part (on-die), in this

      case the phandle should reference the node itself.

      3/ The ECC engine is external, in this case the phandle should

      reference the specific ECC engine node.

    $ref: /schemas/types.yaml#/definitions/phandle



  nand-use-soft-ecc-engine:

    description: Use a software ECC engine.

    type: boolean



  nand-no-ecc-engine:

    description: Do not use any ECC correction.

    type: boolean



  nand-ecc-algo:

    description:

      Desired ECC algorithm.

    $ref: /schemas/types.yaml#/definitions/string

    enum: [hamming, bch, rs]



  nand-ecc-strength:

    description:

      Maximum number of bits that can be corrected per ECC step.

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 1



  nand-ecc-step-size:

    description:

      Number of data bytes covered by a single ECC step.

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 1



  secure-regions:

    description:

      Regions in the NAND chip which are protected using a secure element

      like Trustzone. This property contains the start address and size of

      the secure regions present.

    $ref: /schemas/types.yaml#/definitions/uint64-matrix



required:

  - reg



additionalProperties: true

Documentation/devicetree/bindings/mtd/nand-controller.yaml

+11 −59
Original line number Diff line number Diff line
@@ -39,8 +39,6 @@ properties: 
  ranges: true



  cs-gpios:

    minItems: 1

    maxItems: 8

    description:

      Array of chip-select available to the controller. The first

      entries are a 1:1 mapping of the available chip-select on the
@@ -48,51 +46,27 @@ properties: 
      chip-select as needed may follow and should be phandles of GPIO

      lines. 'reg' entries of the NAND chip subnodes become indexes of

      this array when this property is present.

    minItems: 1

    maxItems: 8



patternProperties:

  "^nand@[a-f0-9]$":

    type: object

    $ref: "nand-chip.yaml#"



    properties:

      reg:

        description:

          Contains the native Ready/Busy IDs.



      nand-ecc-engine:

        allOf:

          - $ref: /schemas/types.yaml#/definitions/phandle

        description: |

          A phandle on the hardware ECC engine if any. There are

          basically three possibilities:

          1/ The ECC engine is part of the NAND controller, in this

          case the phandle should reference the parent node.

          2/ The ECC engine is part of the NAND part (on-die), in this

          case the phandle should reference the node itself.

          3/ The ECC engine is external, in this case the phandle should

          reference the specific ECC engine node.



      nand-use-soft-ecc-engine:

        type: boolean

        description: Use a software ECC engine.



      nand-no-ecc-engine:

        type: boolean

        description: Do not use any ECC correction.

          Contains the chip-select IDs.



      nand-ecc-placement:

        allOf:

          - $ref: /schemas/types.yaml#/definitions/string

          - enum: [ oob, interleaved ]

        description:

          Location of the ECC bytes. This location is unknown by default

          but can be explicitly set to "oob", if all ECC bytes are

          known to be stored in the OOB area, or "interleaved" if ECC

          bytes will be interleaved with regular data in the main area.



      nand-ecc-algo:

        description:

          Desired ECC algorithm.

        $ref: /schemas/types.yaml#/definitions/string

        enum: [hamming, bch, rs]

        enum: [ oob, interleaved ]



      nand-bus-width:

        description:
@@ -102,7 +76,6 @@ patternProperties: 
        default: 8



      nand-on-flash-bbt:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          With this property, the OS will search the device for a Bad

          Block Table (BBT). If not found, it will create one, reserve
@@ -111,21 +84,9 @@ patternProperties: 
          few pages of all the blocks will be scanned at boot time to

          find Bad Block Markers (BBM). These markers will help to

          build a volatile BBT in RAM.



      nand-ecc-strength:

        description:

          Maximum number of bits that can be corrected per ECC step.

        $ref: /schemas/types.yaml#/definitions/uint32

        minimum: 1



      nand-ecc-step-size:

        description:

          Number of data bytes covered by a single ECC step.

        $ref: /schemas/types.yaml#/definitions/uint32

        minimum: 1

        $ref: /schemas/types.yaml#/definitions/flag



      nand-ecc-maximize:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          Whether or not the ECC strength should be maximized. The

          maximum ECC strength is both controller and chip
@@ -134,18 +95,19 @@ patternProperties: 
          constraint into account. This is particularly useful when

          only the in-band area is used by the upper layers, and you

          want to make your NAND as reliable as possible.

        $ref: /schemas/types.yaml#/definitions/flag



      nand-is-boot-medium:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          Whether or not the NAND chip is a boot medium. Drivers might

          use this information to select ECC algorithms supported by

          the boot ROM or similar restrictions.

        $ref: /schemas/types.yaml#/definitions/flag



      nand-rb:

        $ref: /schemas/types.yaml#/definitions/uint32-array

        description:

          Contains the native Ready/Busy IDs.

        $ref: /schemas/types.yaml#/definitions/uint32-array



      rb-gpios:

        description:
@@ -154,13 +116,6 @@ patternProperties: 
          Ready/Busy pins. Active state refers to the NAND ready state and

          should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.



      secure-regions:

        $ref: /schemas/types.yaml#/definitions/uint64-matrix

        description:

          Regions in the NAND chip which are protected using a secure element

          like Trustzone. This property contains the start address and size of

          the secure regions present.



    required:

      - reg
@@ -181,10 +136,7 @@ examples: 


      nand@0 {

        reg = <0>; /* Native CS */

        nand-use-soft-ecc-engine;

        nand-ecc-algo = "bch";



        /* controller specific properties */

        /* NAND chip specific properties */

      };



      nand@1 {

Documentation/devicetree/bindings/mtd/spi-nand.txt

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SPI NAND flash



Required properties:

- compatible: should be "spi-nand"

- reg: should encode the chip-select line used to access the NAND chip

Documentation/devicetree/bindings/mtd/spi-nand.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/spi-nand.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: SPI-NAND flash device tree bindings



maintainers:

  - Miquel Raynal <miquel.raynal@bootlin.com>



allOf:

  - $ref: "nand-chip.yaml#"



properties:

  compatible:

    const: spi-nand



  reg:

    description: Encode the chip-select line on the SPI bus

    maxItems: 1



required:

  - compatible

  - reg



unevaluatedProperties: false